1c960b13eSThomas Chou /* 2c960b13eSThomas Chou * Altera 10/100/1000 triple speed ethernet mac 3c960b13eSThomas Chou * 4c960b13eSThomas Chou * Copyright (C) 2008 Altera Corporation. 5c960b13eSThomas Chou * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> 6c960b13eSThomas Chou * 7c960b13eSThomas Chou * This program is free software; you can redistribute it and/or modify 8c960b13eSThomas Chou * it under the terms of the GNU General Public License version 2 as 9c960b13eSThomas Chou * published by the Free Software Foundation. 10c960b13eSThomas Chou */ 11c960b13eSThomas Chou #ifndef _ALTERA_TSE_H_ 12c960b13eSThomas Chou #define _ALTERA_TSE_H_ 13c960b13eSThomas Chou 1413146ec9SThomas Chou #define __packed_1_ __packed __aligned(1) 15c960b13eSThomas Chou 1638fa4acaSThomas Chou /* dma type */ 1738fa4acaSThomas Chou #define ALT_SGDMA 0 18*e3e87260SThomas Chou #define ALT_MSGDMA 1 1938fa4acaSThomas Chou 20c960b13eSThomas Chou /* SGDMA Stuff */ 214c8df1d3SThomas Chou #define ALT_SGDMA_STATUS_BUSY_MSK BIT(4) 22c960b13eSThomas Chou 234c8df1d3SThomas Chou #define ALT_SGDMA_CONTROL_RUN_MSK BIT(5) 244c8df1d3SThomas Chou #define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK BIT(6) 254c8df1d3SThomas Chou #define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK BIT(16) 26c960b13eSThomas Chou 27c960b13eSThomas Chou /* 28c960b13eSThomas Chou * Descriptor control bit masks & offsets 29c960b13eSThomas Chou * 30c960b13eSThomas Chou * Note: The control byte physically occupies bits [31:24] in memory. 31c960b13eSThomas Chou * The following bit-offsets are expressed relative to the LSB of 32c960b13eSThomas Chou * the control register bitfield. 33c960b13eSThomas Chou */ 344c8df1d3SThomas Chou #define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0) 354c8df1d3SThomas Chou #define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK BIT(1) 364c8df1d3SThomas Chou #define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK BIT(2) 374c8df1d3SThomas Chou #define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK BIT(7) 38c960b13eSThomas Chou 39c960b13eSThomas Chou /* 40c960b13eSThomas Chou * Descriptor status bit masks & offsets 41c960b13eSThomas Chou * 42c960b13eSThomas Chou * Note: The status byte physically occupies bits [23:16] in memory. 43c960b13eSThomas Chou * The following bit-offsets are expressed relative to the LSB of 44c960b13eSThomas Chou * the status register bitfield. 45c960b13eSThomas Chou */ 464c8df1d3SThomas Chou #define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK BIT(7) 47c960b13eSThomas Chou 48c960b13eSThomas Chou /* 49c960b13eSThomas Chou * The SGDMA controller buffer descriptor allocates 50c960b13eSThomas Chou * 64 bits for each address. To support ANSI C, the 51c960b13eSThomas Chou * struct implementing a descriptor places 32-bits 52c960b13eSThomas Chou * of padding directly above each address; each pad must 53c960b13eSThomas Chou * be cleared when initializing a descriptor. 54c960b13eSThomas Chou */ 55c960b13eSThomas Chou 56c960b13eSThomas Chou /* 57c960b13eSThomas Chou * Buffer Descriptor data structure 58c960b13eSThomas Chou * 59c960b13eSThomas Chou */ 60c960b13eSThomas Chou struct alt_sgdma_descriptor { 612cd0a52eSThomas Chou u32 source; /* the address of data to be read. */ 622cd0a52eSThomas Chou u32 source_pad; 63c960b13eSThomas Chou 642cd0a52eSThomas Chou u32 destination; /* the address to write data */ 652cd0a52eSThomas Chou u32 destination_pad; 66c960b13eSThomas Chou 672cd0a52eSThomas Chou u32 next; /* the next descriptor in the list. */ 682cd0a52eSThomas Chou u32 next_pad; 69c960b13eSThomas Chou 702cd0a52eSThomas Chou u16 bytes_to_transfer; /* the number of bytes to transfer */ 712cd0a52eSThomas Chou u8 read_burst; 722cd0a52eSThomas Chou u8 write_burst; 73c960b13eSThomas Chou 742cd0a52eSThomas Chou u16 actual_bytes_transferred;/* bytes transferred by DMA */ 752cd0a52eSThomas Chou u8 descriptor_status; 762cd0a52eSThomas Chou u8 descriptor_control; 77c960b13eSThomas Chou 78c960b13eSThomas Chou } __packed_1_; 79c960b13eSThomas Chou 80c960b13eSThomas Chou /* SG-DMA Control/Status Slave registers map */ 81c960b13eSThomas Chou 82c960b13eSThomas Chou struct alt_sgdma_registers { 832cd0a52eSThomas Chou u32 status; 842cd0a52eSThomas Chou u32 status_pad[3]; 852cd0a52eSThomas Chou u32 control; 862cd0a52eSThomas Chou u32 control_pad[3]; 872cd0a52eSThomas Chou u32 next_descriptor_pointer; 882cd0a52eSThomas Chou u32 descriptor_pad[3]; 89c960b13eSThomas Chou }; 90c960b13eSThomas Chou 91*e3e87260SThomas Chou /* mSGDMA Stuff */ 92*e3e87260SThomas Chou 93*e3e87260SThomas Chou /* mSGDMA extended descriptor format */ 94*e3e87260SThomas Chou struct msgdma_extended_desc { 95*e3e87260SThomas Chou u32 read_addr_lo; /* data buffer source address low bits */ 96*e3e87260SThomas Chou u32 write_addr_lo; /* data buffer destination address low bits */ 97*e3e87260SThomas Chou u32 len; 98*e3e87260SThomas Chou u32 burst_seq_num; 99*e3e87260SThomas Chou u32 stride; 100*e3e87260SThomas Chou u32 read_addr_hi; /* data buffer source address high bits */ 101*e3e87260SThomas Chou u32 write_addr_hi; /* data buffer destination address high bits */ 102*e3e87260SThomas Chou u32 control; /* characteristics of the transfer */ 103*e3e87260SThomas Chou }; 104*e3e87260SThomas Chou 105*e3e87260SThomas Chou /* mSGDMA descriptor control field bit definitions */ 106*e3e87260SThomas Chou #define MSGDMA_DESC_CTL_GEN_SOP BIT(8) 107*e3e87260SThomas Chou #define MSGDMA_DESC_CTL_GEN_EOP BIT(9) 108*e3e87260SThomas Chou #define MSGDMA_DESC_CTL_END_ON_EOP BIT(12) 109*e3e87260SThomas Chou #define MSGDMA_DESC_CTL_END_ON_LEN BIT(13) 110*e3e87260SThomas Chou #define MSGDMA_DESC_CTL_GO BIT(31) 111*e3e87260SThomas Chou 112*e3e87260SThomas Chou /* Tx buffer control flags */ 113*e3e87260SThomas Chou #define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \ 114*e3e87260SThomas Chou MSGDMA_DESC_CTL_GEN_EOP | \ 115*e3e87260SThomas Chou MSGDMA_DESC_CTL_GO) 116*e3e87260SThomas Chou 117*e3e87260SThomas Chou #define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \ 118*e3e87260SThomas Chou MSGDMA_DESC_CTL_END_ON_LEN | \ 119*e3e87260SThomas Chou MSGDMA_DESC_CTL_GO) 120*e3e87260SThomas Chou 121*e3e87260SThomas Chou /* mSGDMA extended descriptor stride definitions */ 122*e3e87260SThomas Chou #define MSGDMA_DESC_TX_STRIDE 0x00010001 123*e3e87260SThomas Chou #define MSGDMA_DESC_RX_STRIDE 0x00010001 124*e3e87260SThomas Chou 125*e3e87260SThomas Chou /* mSGDMA dispatcher control and status register map */ 126*e3e87260SThomas Chou struct msgdma_csr { 127*e3e87260SThomas Chou u32 status; /* Read/Clear */ 128*e3e87260SThomas Chou u32 control; /* Read/Write */ 129*e3e87260SThomas Chou u32 rw_fill_level; 130*e3e87260SThomas Chou u32 resp_fill_level; /* bit 15:0 */ 131*e3e87260SThomas Chou u32 rw_seq_num; 132*e3e87260SThomas Chou u32 pad[3]; /* reserved */ 133*e3e87260SThomas Chou }; 134*e3e87260SThomas Chou 135*e3e87260SThomas Chou /* mSGDMA CSR status register bit definitions */ 136*e3e87260SThomas Chou #define MSGDMA_CSR_STAT_BUSY BIT(0) 137*e3e87260SThomas Chou #define MSGDMA_CSR_STAT_RESETTING BIT(6) 138*e3e87260SThomas Chou #define MSGDMA_CSR_STAT_MASK 0x3FF 139*e3e87260SThomas Chou 140*e3e87260SThomas Chou /* mSGDMA CSR control register bit definitions */ 141*e3e87260SThomas Chou #define MSGDMA_CSR_CTL_RESET BIT(1) 142*e3e87260SThomas Chou 143*e3e87260SThomas Chou /* mSGDMA response register map */ 144*e3e87260SThomas Chou struct msgdma_response { 145*e3e87260SThomas Chou u32 bytes_transferred; 146*e3e87260SThomas Chou u32 status; 147*e3e87260SThomas Chou }; 148*e3e87260SThomas Chou 149c960b13eSThomas Chou /* TSE Stuff */ 1504c8df1d3SThomas Chou #define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0) 1514c8df1d3SThomas Chou #define ALTERA_TSE_CMD_RX_ENA_MSK BIT(1) 1524c8df1d3SThomas Chou #define ALTERA_TSE_CMD_ETH_SPEED_MSK BIT(3) 1534c8df1d3SThomas Chou #define ALTERA_TSE_CMD_HD_ENA_MSK BIT(10) 1544c8df1d3SThomas Chou #define ALTERA_TSE_CMD_SW_RESET_MSK BIT(13) 1554c8df1d3SThomas Chou #define ALTERA_TSE_CMD_ENA_10_MSK BIT(25) 156c960b13eSThomas Chou 15796fa1e43SThomas Chou #define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ) 15896fa1e43SThomas Chou #define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ) 159c960b13eSThomas Chou 160c960b13eSThomas Chou /* MAC register Space */ 161c960b13eSThomas Chou 162c960b13eSThomas Chou struct alt_tse_mac { 1632cd0a52eSThomas Chou u32 megacore_revision; 1642cd0a52eSThomas Chou u32 scratch_pad; 1652cd0a52eSThomas Chou u32 command_config; 1662cd0a52eSThomas Chou u32 mac_addr_0; 1672cd0a52eSThomas Chou u32 mac_addr_1; 1682cd0a52eSThomas Chou u32 max_frame_length; 1692cd0a52eSThomas Chou u32 pause_quanta; 1702cd0a52eSThomas Chou u32 rx_sel_empty_threshold; 1712cd0a52eSThomas Chou u32 rx_sel_full_threshold; 1722cd0a52eSThomas Chou u32 tx_sel_empty_threshold; 1732cd0a52eSThomas Chou u32 tx_sel_full_threshold; 1742cd0a52eSThomas Chou u32 rx_almost_empty_threshold; 1752cd0a52eSThomas Chou u32 rx_almost_full_threshold; 1762cd0a52eSThomas Chou u32 tx_almost_empty_threshold; 1772cd0a52eSThomas Chou u32 tx_almost_full_threshold; 1782cd0a52eSThomas Chou u32 mdio_phy0_addr; 1792cd0a52eSThomas Chou u32 mdio_phy1_addr; 180c960b13eSThomas Chou 1812cd0a52eSThomas Chou u32 reserved1[0x29]; 182c960b13eSThomas Chou 183c960b13eSThomas Chou /*FIFO control register. */ 1842cd0a52eSThomas Chou u32 tx_cmd_stat; 1852cd0a52eSThomas Chou u32 rx_cmd_stat; 186c960b13eSThomas Chou 1872cd0a52eSThomas Chou u32 reserved2[0x44]; 188c960b13eSThomas Chou 189c960b13eSThomas Chou /*Registers 0 to 31 within PHY device 0/1 */ 1902cd0a52eSThomas Chou u32 mdio_phy0[0x20]; 1912cd0a52eSThomas Chou u32 mdio_phy1[0x20]; 192c960b13eSThomas Chou 193c960b13eSThomas Chou /*4 Supplemental MAC Addresses */ 1942cd0a52eSThomas Chou u32 supp_mac_addr_0_0; 1952cd0a52eSThomas Chou u32 supp_mac_addr_0_1; 1962cd0a52eSThomas Chou u32 supp_mac_addr_1_0; 1972cd0a52eSThomas Chou u32 supp_mac_addr_1_1; 1982cd0a52eSThomas Chou u32 supp_mac_addr_2_0; 1992cd0a52eSThomas Chou u32 supp_mac_addr_2_1; 2002cd0a52eSThomas Chou u32 supp_mac_addr_3_0; 2012cd0a52eSThomas Chou u32 supp_mac_addr_3_1; 202c960b13eSThomas Chou 2032cd0a52eSThomas Chou u32 reserved3[0x38]; 204c960b13eSThomas Chou }; 205c960b13eSThomas Chou 20638fa4acaSThomas Chou struct tse_ops { 20738fa4acaSThomas Chou int (*send)(struct udevice *dev, void *packet, int length); 20838fa4acaSThomas Chou int (*recv)(struct udevice *dev, int flags, uchar **packetp); 20938fa4acaSThomas Chou int (*free_pkt)(struct udevice *dev, uchar *packet, int length); 21038fa4acaSThomas Chou void (*stop)(struct udevice *dev); 21138fa4acaSThomas Chou }; 21238fa4acaSThomas Chou 213c960b13eSThomas Chou struct altera_tse_priv { 21496fa1e43SThomas Chou struct alt_tse_mac *mac_dev; 21538fa4acaSThomas Chou void *sgdma_rx; 21638fa4acaSThomas Chou void *sgdma_tx; 21796fa1e43SThomas Chou unsigned int rx_fifo_depth; 21896fa1e43SThomas Chou unsigned int tx_fifo_depth; 21938fa4acaSThomas Chou void *rx_desc; 22038fa4acaSThomas Chou void *tx_desc; 221*e3e87260SThomas Chou void *rx_resp; 22296fa1e43SThomas Chou unsigned char *rx_buf; 223c960b13eSThomas Chou unsigned int phyaddr; 22496fa1e43SThomas Chou unsigned int interface; 22596fa1e43SThomas Chou struct phy_device *phydev; 22696fa1e43SThomas Chou struct mii_dev *bus; 22738fa4acaSThomas Chou const struct tse_ops *ops; 22838fa4acaSThomas Chou int dma_type; 229c960b13eSThomas Chou }; 230c960b13eSThomas Chou 231c960b13eSThomas Chou #endif /* _ALTERA_TSE_H_ */ 232