1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Udoo
4 * Author: Tungyi Lin <tungyilin1127@gmail.com>
5 * Richard Hu <hakahu@gmail.com>
6 * Based on board/wandboard/spl.c
7 */
8
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <linux/errno.h>
14 #include <asm/gpio.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/video.h>
17 #include <mmc.h>
18 #include <fsl_esdhc.h>
19 #include <asm/arch/crm_regs.h>
20 #include <asm/io.h>
21 #include <asm/arch/sys_proto.h>
22 #include <spl.h>
23
24 #if defined(CONFIG_SPL_BUILD)
25 #include <asm/arch/mx6-ddr.h>
26
27 /*
28 * Driving strength:
29 * 0x30 == 40 Ohm
30 * 0x28 == 48 Ohm
31 */
32 #define IMX6DQ_DRIVE_STRENGTH 0x30
33 #define IMX6SDL_DRIVE_STRENGTH 0x28
34
35 /* configure MX6Q/DUAL mmdc DDR io registers */
36 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
37 .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
38 .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
39 .dram_cas = IMX6DQ_DRIVE_STRENGTH,
40 .dram_ras = IMX6DQ_DRIVE_STRENGTH,
41 .dram_reset = IMX6DQ_DRIVE_STRENGTH,
42 .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
43 .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
44 .dram_sdba2 = 0x00000000,
45 .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
46 .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
47 .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
48 .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
49 .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
50 .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
51 .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
52 .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
53 .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
54 .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
55 .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
56 .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
57 .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
58 .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
59 .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
60 .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
61 .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
62 .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
63 };
64
65 /* configure MX6Q/DUAL mmdc GRP io registers */
66 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
67 .grp_ddr_type = 0x000c0000,
68 .grp_ddrmode_ctl = 0x00020000,
69 .grp_ddrpke = 0x00000000,
70 .grp_addds = IMX6DQ_DRIVE_STRENGTH,
71 .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
72 .grp_ddrmode = 0x00020000,
73 .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
74 .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
75 .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
76 .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
77 .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
78 .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
79 .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
80 .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
81 };
82
83 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
84 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
85 .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
86 .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
87 .dram_cas = IMX6SDL_DRIVE_STRENGTH,
88 .dram_ras = IMX6SDL_DRIVE_STRENGTH,
89 .dram_reset = IMX6SDL_DRIVE_STRENGTH,
90 .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
91 .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
92 .dram_sdba2 = 0x00000000,
93 .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
94 .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
95 .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
96 .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
97 .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
98 .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
99 .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
100 .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
101 .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
102 .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
103 .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
104 .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
105 .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
106 .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
107 .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
108 .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
109 .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
110 .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
111 };
112
113 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
114 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
115 .grp_ddr_type = 0x000c0000,
116 .grp_ddrmode_ctl = 0x00020000,
117 .grp_ddrpke = 0x00000000,
118 .grp_addds = IMX6SDL_DRIVE_STRENGTH,
119 .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
120 .grp_ddrmode = 0x00020000,
121 .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
122 .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
123 .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
124 .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
125 .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
126 .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
127 .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
128 .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
129 };
130
131 /* MT41K128M16JT-125 */
132 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
133 /* quad = 1066, duallite = 800 */
134 .mem_speed = 1066,
135 .density = 2,
136 .width = 16,
137 .banks = 8,
138 .rowaddr = 14,
139 .coladdr = 10,
140 .pagesz = 2,
141 .trcd = 1375,
142 .trcmin = 4875,
143 .trasmin = 3500,
144 .SRT = 0,
145 };
146
147 static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
148 .p0_mpwldectrl0 = 0x00350035,
149 .p0_mpwldectrl1 = 0x001F001F,
150 .p1_mpwldectrl0 = 0x00010001,
151 .p1_mpwldectrl1 = 0x00010001,
152 .p0_mpdgctrl0 = 0x43510360,
153 .p0_mpdgctrl1 = 0x0342033F,
154 .p1_mpdgctrl0 = 0x033F033F,
155 .p1_mpdgctrl1 = 0x03290266,
156 .p0_mprddlctl = 0x4B3E4141,
157 .p1_mprddlctl = 0x47413B4A,
158 .p0_mpwrdlctl = 0x42404843,
159 .p1_mpwrdlctl = 0x4C3F4C45,
160 };
161
162 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
163 .p0_mpwldectrl0 = 0x002F0038,
164 .p0_mpwldectrl1 = 0x001F001F,
165 .p1_mpwldectrl0 = 0x001F001F,
166 .p1_mpwldectrl1 = 0x001F001F,
167 .p0_mpdgctrl0 = 0x425C0251,
168 .p0_mpdgctrl1 = 0x021B021E,
169 .p1_mpdgctrl0 = 0x021B021E,
170 .p1_mpdgctrl1 = 0x01730200,
171 .p0_mprddlctl = 0x45474C45,
172 .p1_mprddlctl = 0x44464744,
173 .p0_mpwrdlctl = 0x3F3F3336,
174 .p1_mpwrdlctl = 0x32383630,
175 };
176
177 /* DDR 64bit 1GB */
178 static struct mx6_ddr_sysinfo mem_qdl = {
179 .dsize = 2,
180 .cs1_mirror = 0,
181 /* config for full 4GB range so that get_mem_size() works */
182 .cs_density = 32,
183 .ncs = 1,
184 .bi_on = 1,
185 /* quad = 2, duallite = 1 */
186 .rtt_nom = 2,
187 /* quad = 2, duallite = 1 */
188 .rtt_wr = 2,
189 .ralat = 5,
190 .walat = 0,
191 .mif3_mode = 3,
192 .rst_to_cke = 0x23,
193 .sde_to_rst = 0x10,
194 .refsel = 1, /* Refresh cycles at 32KHz */
195 .refr = 7, /* 8 refresh commands per refresh cycle */
196 };
197
ccgr_init(void)198 static void ccgr_init(void)
199 {
200 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
201
202 /* set the default clock gate to save power */
203 writel(0x00C03F3F, &ccm->CCGR0);
204 writel(0x0030FC03, &ccm->CCGR1);
205 writel(0x0FFFC000, &ccm->CCGR2);
206 writel(0x3FF00000, &ccm->CCGR3);
207 writel(0x00FFF300, &ccm->CCGR4);
208 writel(0x0F0000C3, &ccm->CCGR5);
209 writel(0x000003FF, &ccm->CCGR6);
210 }
211
spl_dram_init(void)212 static void spl_dram_init(void)
213 {
214 if (is_cpu_type(MXC_CPU_MX6DL)) {
215 mt41k128m16jt_125.mem_speed = 800;
216 mem_qdl.rtt_nom = 1;
217 mem_qdl.rtt_wr = 1;
218
219 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
220 mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
221 } else if (is_cpu_type(MXC_CPU_MX6Q)) {
222 mt41k128m16jt_125.mem_speed = 1066;
223 mem_qdl.rtt_nom = 2;
224 mem_qdl.rtt_wr = 2;
225
226 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
227 mx6_dram_cfg(&mem_qdl, &mx6q_1g_mmdc_calib, &mt41k128m16jt_125);
228 }
229
230 udelay(100);
231 }
232
board_init_f(ulong dummy)233 void board_init_f(ulong dummy)
234 {
235 ccgr_init();
236
237 /* setup AIPS and disable watchdog */
238 arch_cpu_init();
239
240 gpr_init();
241
242 /* iomux */
243 board_early_init_f();
244
245 /* setup GP timer */
246 timer_init();
247
248 /* UART clocks enabled and gd valid - init serial console */
249 preloader_console_init();
250
251 /* DDR initialization */
252 spl_dram_init();
253 }
254 #endif
255