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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dgk104.c36 { 0x100d10, 1, 0x0000c244 },
37 { 0x100d30, 1, 0x0000c242 },
38 { 0x100d3c, 1, 0x00000242 },
39 { 0x100d48, 1, 0x00000242 },
40 { 0x100d1c, 1, 0x00000042 },
46 { 0x100c98, 1, 0x00000242 },
52 { 0x10f000, 1, 0x00000042 },
53 { 0x17e030, 1, 0x00000044 },
54 { 0x17e040, 1, 0x00000044 },
60 { 0x17ea60, 4, 0x00000044 },
/openbmc/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.xml.h57 HDCP_KEYS_STATE_NO_KEYS = 0,
68 DDC_WRITE = 0,
73 ACR_NONE = 0,
79 #define REG_HDMI_CTRL 0x00000000
80 #define HDMI_CTRL_ENABLE 0x00000001
81 #define HDMI_CTRL_HDMI 0x00000002
82 #define HDMI_CTRL_ENCRYPTED 0x00000004
84 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
85 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
87 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
[all …]
/openbmc/u-boot/board/compulab/cm_t43/
H A Dspl.c29 .emif_sdram_config_ext = 0x0143,
34 .sdram_config = 0x638413B2,
35 .ref_ctrl = 0x00000C30,
36 .sdram_tim1 = 0xEAAAD4DB,
37 .sdram_tim2 = 0x266B7FDA,
38 .sdram_tim3 = 0x107F8678,
39 .read_idle_ctrl = 0x00050000,
40 .zq_config = 0x50074BE4,
41 .temp_alert_config = 0x0,
42 .emif_ddr_phy_ctlr_1 = 0x0E004008,
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dcs35l45-tables.c15 { 0x00000040, 0x00000055 },
16 { 0x00000040, 0x000000AA },
17 { 0x00000044, 0x00000055 },
18 { 0x00000044, 0x000000AA },
19 { 0x00006480, 0x0830500A },
20 { 0x00007C60, 0x1000850B },
21 { CS35L45_BOOST_OV_CFG, 0x007000D0 },
22 { CS35L45_LDPM_CONFIG, 0x0001B636 },
23 { 0x00002C08, 0x00000009 },
24 { 0x00006850, 0x0A30FFC4 },
[all …]
/openbmc/linux/drivers/gpu/drm/msm/dp/
H A Ddp_reg.h10 #define REG_DP_HW_VERSION (0x00000000)
12 #define REG_DP_SW_RESET (0x00000010)
13 #define DP_SW_RESET (0x00000001)
15 #define REG_DP_PHY_CTRL (0x00000014)
16 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
17 #define DP_PHY_CTRL_SW_RESET (0x00000004)
19 #define REG_DP_CLK_CTRL (0x00000018)
20 #define REG_DP_CLK_ACTIVE (0x0000001C)
21 #define REG_DP_INTR_STATUS (0x00000020)
22 #define REG_DP_INTR_STATUS2 (0x00000024)
[all …]
/openbmc/linux/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI (1 << 0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/openbmc/u-boot/include/
H A Dmb862xx.h14 #define PCI_VENDOR_ID_FUJITSU 0x10CF
15 #define PCI_DEVICE_ID_CORAL_P 0x2019
16 #define PCI_DEVICE_ID_CORAL_PA 0x201E
18 #define MB862XX_TYPE_LIME 0x1
20 #define GC_HOST_BASE 0x01fc0000
21 #define GC_DISP_BASE 0x01fd0000
22 #define GC_DRAW_BASE 0x01ff0000
25 #define GC_SRST 0x0000002c
26 #define GC_CCF 0x00000038
27 #define GC_CID 0x000000f0
[all …]
/openbmc/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_phy_28nm_8960.xml.h56 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN()
58 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0()
60 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1()
62 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2()
64 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x… in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH()
66 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0()
68 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1()
70 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
72 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
74 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
[all …]
H A Ddsi_phy_14nm.xml.h56 #define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
58 #define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
60 #define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
62 #define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
64 #define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
65 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
71 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
78 #define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
79 #define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
81 #define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl006c.h27 #define NV06C_PUT (0x00000040)
29 #define NV06C_GET (0x00000044)
37 #define NV06C_OPCODE_METHOD (0x00000000)
38 #define NV06C_OPCODE_NONINC_METHOD (0x00000002)
41 #define NV06C_DATA 31:0
44 #define NV06C_OPCODE_JUMP (0x00000001)
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9330_1p2_initvals.h45 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
46 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
47 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
48 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
49 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
50 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
51 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
52 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
53 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
54 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
[all …]
H A Dar9330_1p1_initvals.h27 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
28 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
29 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
30 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
31 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
32 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
33 {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
34 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
35 {0x00009e04, 0x00202020, 0x00202020, 0x00202020, 0x00202020},
36 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
[all …]
/openbmc/qemu/tests/tcg/hppa/
H A Dstby.c18 int err = 0; in check()
20 if (s->a != 0) { in check()
21 fprintf(stderr, "%s %s %d: garbage before word 0x%08x\n", in check()
25 if (s->c != 0) { in check()
26 fprintf(stderr, "%s %s %d: garbage after word 0x%08x\n", in check()
31 fprintf(stderr, "%s %s %d: 0x%08x != 0x%08x\n", in check()
43 s.b = 0; \
44 asm volatile(INSN " %1, " #OFS "(%0)" \
45 : : "r"(&s.b), "r" (0x11223344) : "memory"); \
47 } while (0)
[all …]
/openbmc/linux/drivers/gpu/drm/tegra/
H A Dfalcon.h11 #define FALCON_UCLASS_METHOD_OFFSET 0x00000040
13 #define FALCON_UCLASS_METHOD_DATA 0x00000044
15 #define FALCON_IRQMSET 0x00001010
21 #define FALCON_IRQMSET_EXT(v) (((v) & 0xff) << 8)
23 #define FALCON_IRQDEST 0x0000101c
28 #define FALCON_IRQDEST_EXT(v) (((v) & 0xff) << 8)
30 #define FALCON_ITFEN 0x00001048
31 #define FALCON_ITFEN_CTXEN (1 << 0)
34 #define FALCON_IDLESTATE 0x0000104c
36 #define FALCON_CPUCTL 0x00001100
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/dram/
H A Dumc-regs.h13 #define UMC_CPURST 0x00000700
14 #define UMC_IDSRST 0x0000070C
15 #define UMC_IXMRST 0x00000714
16 #define UMC_HDMRST 0x00000718
17 #define UMC_MDMRST 0x0000071C
18 #define UMC_HDDRST 0x00000720
19 #define UMC_MDDRST 0x00000724
20 #define UMC_SIORST 0x00000728
21 #define UMC_GIORST 0x0000072C
22 #define UMC_HD2RST 0x00000734
[all …]
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_0.c57 #define SDMA1_REG_OFFSET 0x600
58 #define SDMA0_HYP_DEC_REG_START 0x5880
59 #define SDMA0_HYP_DEC_REG_END 0x5893
60 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
[all …]
/openbmc/u-boot/board/maxbcm/
H A Dmaxbcm.c19 #define DEV_CS0_BASE 0xe0000000
20 #define DEV_CS1_BASE 0xe1000000
21 #define DEV_CS2_BASE 0xe2000000
22 #define DEV_CS3_BASE 0xe3000000
26 {0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */
27 {0x00001404, 0x30000820}, /* Dunit Control Low Register */
28 {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */
29 {0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */
30 {0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */
31 {0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */
[all …]
/openbmc/linux/drivers/crypto/amcc/
H A Dcrypto4xx_reg_def.h15 #define CRYPTO4XX_DESCRIPTOR 0x00000000
16 #define CRYPTO4XX_CTRL_STAT 0x00000000
17 #define CRYPTO4XX_SOURCE 0x00000004
18 #define CRYPTO4XX_DEST 0x00000008
19 #define CRYPTO4XX_SA 0x0000000C
20 #define CRYPTO4XX_SA_LENGTH 0x00000010
21 #define CRYPTO4XX_LENGTH 0x00000014
23 #define CRYPTO4XX_PE_DMA_CFG 0x00000040
24 #define CRYPTO4XX_PE_DMA_STAT 0x00000044
25 #define CRYPTO4XX_PDR_BASE 0x00000048
[all …]
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg19 # Configure RGMII-0 interface pad voltage to 1.8V
20 DATA 0xFFD100e0 0x1B1B1B9B
23 DATA 0xFFD01400 0x43000C30 # DDR Configuration register
24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
31 DATA 0xFFD01404 0x38743000 # DDR Controller Control Low
32 # bit 4: 0=addr/cmd in smame cycle
33 # bit 5: 0=clk is driven during self refresh, we don't care for APX
34 # bit 6: 0=use recommended falling edge of clk for addr/cmd
35 # bit14: 0=input buffer always powered up
37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
[all …]
/openbmc/linux/include/linux/platform_data/
H A Dsh_mmcif.h31 u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
36 #define MMCIF_CE_CMD_SET 0x00000000
37 #define MMCIF_CE_ARG 0x00000008
38 #define MMCIF_CE_ARG_CMD12 0x0000000C
39 #define MMCIF_CE_CMD_CTRL 0x00000010
40 #define MMCIF_CE_BLOCK_SET 0x00000014
41 #define MMCIF_CE_CLK_CTRL 0x00000018
42 #define MMCIF_CE_BUF_ACC 0x0000001C
43 #define MMCIF_CE_RESP3 0x00000020
44 #define MMCIF_CE_RESP2 0x00000024
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
H A Dnv50.c42 if (ret == 0) { in nv50_mpeg_cclass_bind()
44 nvkm_wo32(*pgpuobj, 0x70, 0x00801ec1); in nv50_mpeg_cclass_bind()
45 nvkm_wo32(*pgpuobj, 0x7c, 0x0000037c); in nv50_mpeg_cclass_bind()
65 u32 stat = nvkm_rd32(device, 0x00b100); in nv50_mpeg_intr()
66 u32 type = nvkm_rd32(device, 0x00b230); in nv50_mpeg_intr()
67 u32 mthd = nvkm_rd32(device, 0x00b234); in nv50_mpeg_intr()
68 u32 data = nvkm_rd32(device, 0x00b238); in nv50_mpeg_intr()
71 if (stat & 0x01000000) { in nv50_mpeg_intr()
73 if (type == 0x00000020 && mthd == 0x0000) { in nv50_mpeg_intr()
74 nvkm_wr32(device, 0x00b308, 0x00000100); in nv50_mpeg_intr()
[all …]
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage.cfg12 DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
13 # bit 3-0: MPPSel0 2, NF_IO[2]
20 # bit 31-28: MPPSel7 0, GPO[7]
22 DATA 0xFFD10004 0x03303300
24 DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
25 # bit 3-0: MPPSel16 0, GPIO[16]
26 # bit 7-4: MPPSel17 0, GPIO[17]
27 # bit 12-8: MPPSel18 1, NF_IO[0]
29 # bit 19-16: MPPSel20 0, GPIO[20]
30 # bit 23-20: MPPSel21 0, GPIO[21]
[all …]
/openbmc/u-boot/board/Synology/ds414/
H A Dds414.c24 #define DS414_GPP_OUT_VAL_HIGH (0)
26 #define DS414_GPP_OUT_POL_LOW (0)
27 #define DS414_GPP_OUT_POL_MID (0)
28 #define DS414_GPP_OUT_POL_HIGH (0)
33 #define DS414_GPP_OUT_ENA_HIGH (~0)
36 0x11111111,
37 0x22221111,
38 0x22222222,
39 0x00000000,
40 0x11110000,
[all …]
/openbmc/u-boot/board/armltd/integrator/
H A Dpci_v3.h23 #define V3_PCI_VENDOR 0x00000000
24 #define V3_PCI_DEVICE 0x00000002
25 #define V3_PCI_CMD 0x00000004
26 #define V3_PCI_STAT 0x00000006
27 #define V3_PCI_CC_REV 0x00000008
28 #define V3_PCI_HDR_CFG 0x0000000C
29 #define V3_PCI_IO_BASE 0x00000010
30 #define V3_PCI_BASE0 0x00000014
31 #define V3_PCI_BASE1 0x00000018
32 #define V3_PCI_SUB_VENDOR 0x0000002C
[all …]

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