board/maxbcm/maxbcm.c

19 #define DEV_CS0_BASE		0xe0000000
20 #define DEV_CS1_BASE		0xe1000000
21 #define DEV_CS2_BASE		0xe2000000
22 #define DEV_CS3_BASE		0xe3000000
26 	{0x00001400, 0x7301CC30},	/* DDR SDRAM Configuration Register */
27 	{0x00001404, 0x30000820},	/* Dunit Control Low Register */
28 	{0x00001408, 0x5515BAAB},	/* DDR SDRAM Timing (Low) Register */
29 	{0x0000140C, 0x38DA3F97},	/* DDR SDRAM Timing (High) Register */
30 	{0x00001410, 0x20100005},	/* DDR SDRAM Address Control Register */
31 	{0x00001414, 0x0000F3FF},	/* DDR SDRAM Open Pages Control Reg */
32 	{0x00001418, 0x00000e00},	/* DDR SDRAM Operation Register */
33 	{0x0000141C, 0x00000672},	/* DDR SDRAM Mode Register */
34 	{0x00001420, 0x00000004},	/* DDR SDRAM Extended Mode Register */
35 	{0x00001424, 0x0000F3FF},	/* Dunit Control High Register */
36 	{0x00001428, 0x0011A940},	/* Dunit Control High Register */
37 	{0x0000142C, 0x014C5134},	/* Dunit Control High Register */
38 	{0x0000147C, 0x0000D771},
40 	{0x00001494, 0x00010000},	/* DDR SDRAM ODT Control (Low) Reg */
41 	{0x0000149C, 0x00000001},	/* DDR Dunit ODT Control Register */
42 	{0x000014A0, 0x00000001},
43 	{0x000014A8, 0x00000101},
46 	{0x000014C0, 0x192424C9},	/* DRAM addr and Ctrl Driving Strenght*/
47 	{0x000014C4, 0xAAA24C9},	/* DRAM Data and DQS Driving Strenght */
53 	{0x000200e8, 0x3FFF0E01},
54 	{0x00020184, 0x3FFFFFE0},	/* Close fast path Window to - 2G */
56 	{0x0001504, 0x3FFFFFE1},	/* CS0 Size */
57 	{0x000150C, 0x00000000},	/* CS1 Size */
58 	{0x0001514, 0x00000000},	/* CS2 Size */
59 	{0x000151C, 0x00000000},	/* CS3 Size */
61 	{0x0020220, 0x00000007},	/* Reserved */
63 	{0x00001538, 0x0000000B},	/* Read Data Sample Delays Register */
64 	{0x0000153C, 0x0000000B},	/* Read Data Ready Delay Register */
66 	{0x000015D0, 0x00000670},	/* MR0 */
67 	{0x000015D4, 0x00000044},	/* MR1 */
68 	{0x000015D8, 0x00000018},	/* MR2 */
69 	{0x000015DC, 0x00000000},	/* MR3 */
70 	{0x000015E0, 0x00000001},
71 	{0x000015E4, 0x00203c18},	/* ZQDS Configuration Register */
72 	{0x000015EC, 0xF800A225},	/* DDR PHY */
74 	{0x0, 0x0}
78 	{"maxbcm_1600-800", 0xB, 0x5, 0x0, A0, ddr3_b0_maxbcm,  NULL},
83 /* MAXBCM: SERDES 0-4 PCIE, Serdes 7 = SGMII 0, all others =  unconnected */
85 	{ MV_PEX_ROOT_COMPLEX, 0x20011111, 0x00000000,
88 	  0x1f, serdes_change_m_phy
95 	return &maxbcm_ddr_modes[0];  in ddr3_get_static_ddr_mode()
100 	return &maxbcm_serdes_cfg[0];  in board_serdes_cfg_get()
122 	return 0;  in board_early_init_f()
128 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;  in board_init()
130 	return 0;  in board_init()
137 	return 0;  in checkboard()
150 	return 0;  in board_phy_config()