Lines Matching +full:0 +full:x00000044
57 #define SDMA1_REG_OFFSET 0x600
58 #define SDMA0_HYP_DEC_REG_START 0x5880
59 #define SDMA0_HYP_DEC_REG_END 0x5893
60 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
89 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
90 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
173 base = adev->reg_offset[GC_HWIP][0][1]; in sdma_v5_0_get_reg_offset()
177 base = adev->reg_offset[GC_HWIP][0][0]; in sdma_v5_0_get_reg_offset()
187 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_0_init_golden_registers()
188 case IP_VERSION(5, 0, 0): in sdma_v5_0_init_golden_registers()
196 case IP_VERSION(5, 0, 2): in sdma_v5_0_init_golden_registers()
204 case IP_VERSION(5, 0, 5): in sdma_v5_0_init_golden_registers()
217 case IP_VERSION(5, 0, 1): in sdma_v5_0_init_golden_registers()
234 * Returns 0 on success, error on failure.
243 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_init_microcode()
261 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ in sdma_v5_0_ring_init_cond_exec()
272 BUG_ON(ring->ring[offset] != 0x55aa55aa); in sdma_v5_0_ring_patch_cond_exec()
295 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); in sdma_v5_0_ring_get_rptr()
314 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v5_0_ring_get_wptr()
319 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); in sdma_v5_0_ring_get_wptr()
354 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", in sdma_v5_0_ring_set_wptr()
358 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", in sdma_v5_0_ring_set_wptr()
369 "wptr_offs == 0x%08x " in sdma_v5_0_ring_set_wptr()
370 "lower_32_bits(ring->wptr) << 2 == 0x%08x " in sdma_v5_0_ring_set_wptr()
371 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", in sdma_v5_0_ring_set_wptr()
378 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", in sdma_v5_0_ring_set_wptr()
383 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " in sdma_v5_0_ring_set_wptr()
384 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", in sdma_v5_0_ring_set_wptr()
404 for (i = 0; i < count; i++) in sdma_v5_0_ring_insert_nop()
405 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_0_ring_insert_nop()
434 * wptr + 6 + x = 8k, k >= 0, which in C is, in sdma_v5_0_ring_emit_ib()
435 * (wptr + 6 + x) % 8 = 0. in sdma_v5_0_ring_emit_ib()
441 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); in sdma_v5_0_ring_emit_ib()
443 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
465 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); in sdma_v5_0_ring_emit_mem_sync()
467 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); in sdma_v5_0_ring_emit_mem_sync()
468 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | in sdma_v5_0_ring_emit_mem_sync()
470 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | in sdma_v5_0_ring_emit_mem_sync()
471 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); in sdma_v5_0_ring_emit_mem_sync()
484 u32 ref_and_mask = 0; in sdma_v5_0_ring_emit_hdp_flush()
487 if (ring->me == 0) in sdma_v5_0_ring_emit_hdp_flush()
499 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | in sdma_v5_0_ring_emit_hdp_flush()
521 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ in sdma_v5_0_ring_emit_fence()
523 BUG_ON(addr & 0x3); in sdma_v5_0_ring_emit_fence()
532 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); in sdma_v5_0_ring_emit_fence()
534 BUG_ON(addr & 0x3); in sdma_v5_0_ring_emit_fence()
542 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; in sdma_v5_0_ring_emit_fence()
564 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_stop()
566 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_0_gfx_stop()
569 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); in sdma_v5_0_gfx_stop()
596 u32 f32_cntl = 0, phase_quantum = 0; in sdma_v5_0_ctx_switch_enable()
601 unsigned unit = 0; in sdma_v5_0_ctx_switch_enable()
623 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_ctx_switch_enable()
627 AUTO_CTXSW_ENABLE, enable ? 1 : 0); in sdma_v5_0_ctx_switch_enable()
665 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_enable()
667 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v5_0_enable()
678 * Returns 0 for success, error for failure.
692 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_resume()
696 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); in sdma_v5_0_gfx_resume()
710 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_0_gfx_resume()
711 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); in sdma_v5_0_gfx_resume()
712 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_0_gfx_resume()
713 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); in sdma_v5_0_gfx_resume()
731 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); in sdma_v5_0_gfx_resume()
733 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); in sdma_v5_0_gfx_resume()
742 ring->wptr = 0; in sdma_v5_0_gfx_resume()
763 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); in sdma_v5_0_gfx_resume()
775 /* set minor_ptr_update to 0 after wptr programed */ in sdma_v5_0_gfx_resume()
776 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); in sdma_v5_0_gfx_resume()
796 temp &= 0xFF0FFF; in sdma_v5_0_gfx_resume()
804 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); in sdma_v5_0_gfx_resume()
833 return 0; in sdma_v5_0_gfx_resume()
842 * Returns 0 for success, error for failure.
846 return 0; in sdma_v5_0_rlc_resume()
855 * Returns 0 for success, -EINVAL if the ucode is not available.
867 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_load_microcode()
879 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); in sdma_v5_0_load_microcode()
881 for (j = 0; j < fw_size; j++) { in sdma_v5_0_load_microcode()
882 if (amdgpu_emu_mode == 1 && j % 500 == 0) in sdma_v5_0_load_microcode()
890 return 0; in sdma_v5_0_load_microcode()
899 * Returns 0 for success, error for failure.
903 int r = 0; in sdma_v5_0_start()
949 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0, in sdma_v5_0_mqd_init()
960 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0, in sdma_v5_0_mqd_init()
966 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1); in sdma_v5_0_mqd_init()
968 return 0; in sdma_v5_0_mqd_init()
984 * Returns 0 for success, error for failure.
996 tmp = 0xCAFEDEAD; in sdma_v5_0_ring_test_ring()
999 uint32_t offset = 0; in sdma_v5_0_ring_test_ring()
1027 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); in sdma_v5_0_ring_test_ring()
1028 amdgpu_ring_write(ring, 0xDEADBEEF); in sdma_v5_0_ring_test_ring()
1031 for (i = 0; i < adev->usec_timeout; i++) { in sdma_v5_0_ring_test_ring()
1036 if (tmp == 0xDEADBEEF) in sdma_v5_0_ring_test_ring()
1060 * Returns 0 on success, error on failure.
1069 u32 tmp = 0; in sdma_v5_0_ring_test_ib()
1073 tmp = 0xCAFEDEAD; in sdma_v5_0_ring_test_ib()
1074 memset(&ib, 0, sizeof(ib)); in sdma_v5_0_ring_test_ib()
1077 uint32_t offset = 0; in sdma_v5_0_ring_test_ib()
1105 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | in sdma_v5_0_ring_test_ib()
1109 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); in sdma_v5_0_ring_test_ib()
1110 ib.ptr[4] = 0xDEADBEEF; in sdma_v5_0_ring_test_ib()
1121 if (r == 0) { in sdma_v5_0_ring_test_ib()
1125 } else if (r < 0) { in sdma_v5_0_ring_test_ib()
1135 if (tmp == 0xDEADBEEF) in sdma_v5_0_ring_test_ib()
1136 r = 0; in sdma_v5_0_ring_test_ib()
1169 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in sdma_v5_0_vm_copy_pte()
1199 for (; ndw > 0; ndw -= 2) { in sdma_v5_0_vm_write_pte()
1232 ib->ptr[ib->length_dw++] = 0; in sdma_v5_0_vm_set_pte_pde()
1249 pad_count = (-ib->length_dw) & 0x7; in sdma_v5_0_ring_pad_ib()
1250 for (i = 0; i < pad_count; i++) in sdma_v5_0_ring_pad_ib()
1251 if (sdma && sdma->burst_nop && (i == 0)) in sdma_v5_0_ring_pad_ib()
1275 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | in sdma_v5_0_ring_emit_pipeline_sync()
1278 amdgpu_ring_write(ring, addr & 0xfffffffc); in sdma_v5_0_ring_emit_pipeline_sync()
1279 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); in sdma_v5_0_ring_emit_pipeline_sync()
1281 amdgpu_ring_write(ring, 0xffffffff); /* mask */ in sdma_v5_0_ring_emit_pipeline_sync()
1282 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | in sdma_v5_0_ring_emit_pipeline_sync()
1307 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); in sdma_v5_0_ring_emit_wreg()
1316 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | in sdma_v5_0_ring_emit_reg_wait()
1319 amdgpu_ring_write(ring, 0); in sdma_v5_0_ring_emit_reg_wait()
1322 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | in sdma_v5_0_ring_emit_reg_wait()
1332 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); in sdma_v5_0_ring_emit_reg_write_reg_wait()
1346 return 0; in sdma_v5_0_early_init()
1376 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_sw_init()
1384 ring->doorbell_index = (i == 0) ? in sdma_v5_0_sw_init()
1385 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset in sdma_v5_0_sw_init()
1388 ring->vm_hub = AMDGPU_GFXHUB(0); in sdma_v5_0_sw_init()
1391 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : in sdma_v5_0_sw_init()
1406 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v5_0_sw_fini()
1411 return 0; in sdma_v5_0_sw_fini()
1433 return 0; in sdma_v5_0_hw_fini()
1439 return 0; in sdma_v5_0_hw_fini()
1461 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_is_idle()
1477 for (i = 0; i < adev->usec_timeout; i++) { in sdma_v5_0_wait_for_idle()
1478 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); in sdma_v5_0_wait_for_idle()
1482 return 0; in sdma_v5_0_wait_for_idle()
1492 return 0; in sdma_v5_0_soft_reset()
1497 int i, r = 0; in sdma_v5_0_ring_preempt_ib()
1499 u32 index = 0; in sdma_v5_0_ring_preempt_ib()
1503 if (index == 0) in sdma_v5_0_ring_preempt_ib()
1515 ring->trail_seq, 0); in sdma_v5_0_ring_preempt_ib()
1522 for (i = 0; i < adev->usec_timeout; i++) { in sdma_v5_0_ring_preempt_ib()
1535 WREG32(sdma_gfx_preempt, 0); in sdma_v5_0_ring_preempt_ib()
1551 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : in sdma_v5_0_set_trap_irq_state()
1556 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in sdma_v5_0_set_trap_irq_state()
1560 return 0; in sdma_v5_0_set_trap_irq_state()
1567 uint32_t mes_queue_id = entry->src_data[0]; in sdma_v5_0_process_trap_irq()
1583 return 0; in sdma_v5_0_process_trap_irq()
1589 case 0: in sdma_v5_0_process_trap_irq()
1590 amdgpu_fence_process(&adev->sdma.instance[0].ring); in sdma_v5_0_process_trap_irq()
1605 case 0: in sdma_v5_0_process_trap_irq()
1620 return 0; in sdma_v5_0_process_trap_irq()
1627 return 0; in sdma_v5_0_process_illegal_inst_irq()
1636 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_update_medium_grain_clock_gating()
1673 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_update_medium_grain_light_sleep()
1698 return 0; in sdma_v5_0_set_clockgating_state()
1700 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_0_set_clockgating_state()
1701 case IP_VERSION(5, 0, 0): in sdma_v5_0_set_clockgating_state()
1702 case IP_VERSION(5, 0, 2): in sdma_v5_0_set_clockgating_state()
1703 case IP_VERSION(5, 0, 5): in sdma_v5_0_set_clockgating_state()
1713 return 0; in sdma_v5_0_set_clockgating_state()
1719 return 0; in sdma_v5_0_set_powergating_state()
1728 *flags = 0; in sdma_v5_0_get_clockgating_state()
1731 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); in sdma_v5_0_get_clockgating_state()
1736 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); in sdma_v5_0_get_clockgating_state()
1761 .align_mask = 0xf,
1800 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_set_ring_funcs()
1844 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); in sdma_v5_0_emit_copy_buffer()
1846 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ in sdma_v5_0_emit_copy_buffer()
1876 .copy_max_bytes = 0x400000,
1880 .fill_max_bytes = 0x400000,
1889 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; in sdma_v5_0_set_buffer_funcs()
1906 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_set_vm_pte_funcs()
1917 .minor = 0,
1918 .rev = 0,