Lines Matching +full:0 +full:x00000044
56 #define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
58 #define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
60 #define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
62 #define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
64 #define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
65 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
71 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
78 #define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
79 #define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
81 #define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
82 #define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
84 #define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
86 #define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
88 #define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
90 #define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
92 #define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
94 #define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
96 #define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
98 #define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
100 #define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
102 #define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
104 #define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
106 #define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
107 #define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
109 #define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
110 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
111 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
117 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_14nm_PHY_LN()
119 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG0()
120 #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
127 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG1()
128 #define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
130 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG2()
132 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG3()
134 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TEST_DATAPATH()
136 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_TEST_STR()
138 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_4()
139 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
140 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
146 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_5()
147 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
148 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
154 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_6()
155 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
156 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
162 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_7()
163 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
164 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
170 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_8()
171 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
172 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
178 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_9()
179 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
180 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
185 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
192 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_10()
193 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
194 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
200 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_11()
201 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
202 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
208 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*… in REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0()
210 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*… in REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1()
212 static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_VREG_CNTRL()
214 #define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
216 #define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
218 #define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
220 #define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
222 #define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
224 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
226 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
228 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
230 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
232 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
234 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
236 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
238 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
240 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
242 #define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
244 #define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
246 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
248 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
250 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
252 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
254 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
256 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
258 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
260 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
262 #define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
264 #define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
266 #define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
268 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
270 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
272 #define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
274 #define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
276 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
278 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
280 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
282 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
284 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
286 #define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
288 #define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
290 #define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
292 #define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
294 #define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
296 #define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
298 #define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
300 #define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
302 #define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
304 #define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
306 #define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108