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/openbmc/u-boot/include/bedbug/
H A Dtables.h16 /*----- ------ ----- ----- ---- ------------ */
18 { O_BD, "O_BD", 14, 2, OH_ADDR }, /* 16-29 */
19 { O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */
20 { O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */
21 { O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */
22 { O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */
23 { O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */
24 { O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */
25 { O_d, "O_d", 15, 0, OH_OFFSET }, /* 16-31 */
26 { O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl502d.h2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_WAIT_FOR_IDLE 0x0110
30 …_WAIT_FOR_IDLE_V 31:0
32 …_SET_DST_CONTEXT_DMA 0x0184
33 …_SET_DST_CONTEXT_DMA_HANDLE 31:0
35 …_SET_SRC_CONTEXT_DMA 0x0188
36 …_SET_SRC_CONTEXT_DMA_HANDLE 31:0
38 …_SET_SEMAPHORE_CONTEXT_DMA 0x018c
[all …]
H A Dcl5039.h2 * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_NO_OPERATION 0x0100
30 …_NO_OPERATION_V 31:0
32 …_SET_CONTEXT_DMA_NOTIFY 0x0180
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
35 …_SET_CONTEXT_DMA_BUFFER_IN 0x0184
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
38 …_SET_CONTEXT_DMA_BUFFER_OUT 0x0188
[all …]
H A Dcl902d.h2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_CLASS_ID 15:0
30 …_WAIT_FOR_IDLE 0x0110
31 …_WAIT_FOR_IDLE_V 31:0
33 …_SET_DST_FORMAT 0x0200
34 …_SET_DST_FORMAT_V 7:0
35 …_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF
36 …_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0
37 …_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF
[all …]
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-vsp1-hgo.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
[all …]
/openbmc/linux/drivers/net/dsa/sja1105/
H A Dsja1105_ethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
90 /* MAC-Level Diagnostic Counters */
94 .offset = 0,
95 .start = 31,
101 .offset = 0x0,
108 .offset = 0x0,
115 .offset = 0x0,
117 .end = 0,
119 /* MAC-Level Diagnostic Flags */
[all …]
/openbmc/linux/arch/powerpc/lib/
H A Dfeature-fixups-test.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 #include <asm/feature-fixups.h>
9 #include <asm/asm-compat.h>
10 #include <asm/ppc-opcode.h>
48 or 31,31,31
52 or 31,31,31
68 or 31,31,31
69 or 31,31,31
83 or 31,31,31
84 or 31,31,31
[all …]
/openbmc/linux/arch/powerpc/xmon/
H A Dppc-opc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
27 inserting operands into instructions and vice-versa is kept in this
135 #define UNUSED 0
136 { 0, 0, NULL, NULL, 0 },
142 #define BI_MASK (0x1f << 16)
143 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
148 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
152 #define BB_MASK (0x1f << 11)
[all …]
/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/
H A Ddr_ste_v2.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
7 DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_0 = 0x00,
8 DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_1 = 0x01,
9 DR_STE_V2_ACTION_MDFY_FLD_L2_OUT_2 = 0x02,
10 DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_0 = 0x08,
11 DR_STE_V2_ACTION_MDFY_FLD_SRC_L2_OUT_1 = 0x09,
12 DR_STE_V2_ACTION_MDFY_FLD_L3_OUT_0 = 0x0e,
13 DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_0 = 0x18,
14 DR_STE_V2_ACTION_MDFY_FLD_L4_OUT_1 = 0x19,
15 DR_STE_V2_ACTION_MDFY_FLD_IPV4_OUT_0 = 0x40,
[all …]
/openbmc/linux/drivers/video/fbdev/nvidia/
H A Dnv_dma.h8 |* hereby granted a nonexclusive, royalty-free copyright license to *|
11 |* Any use of this source code must include, in the user documenta- *|
19 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
21 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
23 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
24 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
33 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
35 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
42 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
43 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
23 MT_HIF0 = 0x0,
25 MT_LMAC_AC00 = 0x0,
29 MT_LMAC_ALTX0 = 0x10,
35 #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
37 #define MT_TX_FREE_COUNT GENMASK(12, 0)
38 /* 0: success, others: dropped */
41 #define MT_TX_FREE_PAIR BIT(31)
43 #define MT_TX_FREE_RATE GENMASK(13, 0)
45 #define MT_TXD0_Q_IDX GENMASK(31, 25)
[all …]
H A Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
9 MT_HIF0 = 0x0,
11 MT_LMAC_AC00 = 0x0,
15 MT_LMAC_ALTX0 = 0x10,
24 #define MT_RXD0_LENGTH GENMASK(15, 0)
26 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
34 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
35 #define MT_RXD0_SW_PKT_TYPE_MAP 0x380F
36 #define MT_RXD0_SW_PKT_TYPE_FRAME 0x3801
39 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(11, 0)
[all …]
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-ciu2-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 …ine CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * …
32 …ine CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * …
33 … CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * …
34 …CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * …
35 …CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * …
36 …_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * …
37 …_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * …
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-clk-ccf.dtsi1 // SPDX-License-Identifier: GPL-2.0+
36 u-boot,dm-pre-reloc;
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <33333333>;
43 u-boot,dm-pre-reloc;
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <27000000>;
50 u-boot,dm-pre-reloc;
[all …]
/openbmc/linux/arch/powerpc/crypto/
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
16 # clamp r &= 0x0FFFFFFC0FFFFFFC 0x0FFFFFFC0FFFFFFF
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
[all …]
/openbmc/openbmc/poky/meta/recipes-devtools/binutils/binutils/
H A D0007-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch3 Date: Sat, 11 Jun 2016 22:08:29 -0500
6 The wait mnemonic for ppc targets is incorrectly assembled into 0x7c00003c due
10 Upstream-Status: Pending
11 Signed-off-by: Zhenhua Luo <zhenhua.luo@nxp.com>
12 ---
13 opcodes/ppc-opc.c | 4 +---
14 1 file changed, 1 insertion(+), 3 deletions(-)
16 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
18 --- a/opcodes/ppc-opc.c
19 +++ b/opcodes/ppc-opc.c
[all …]
/openbmc/u-boot/drivers/ram/
H A Dmpc83xx_sdram.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <dt-bindings/memory/mpc83xx-sdram.h>
15 static const u32 CSCONFIG_ENABLE = 0x80000000;
18 static const u32 BANK_BITS_3 = 0x00004000;
21 static const u32 ROW_BITS_13 = 0x00000100;
22 static const u32 ROW_BITS_14 = 0x00000200;
25 static const u32 COL_BITS_9 = 0x00000001;
26 static const u32 COL_BITS_10 = 0x00000002;
27 static const u32 COL_BITS_11 = 0x00000003;
30 static const uint TIMING_CFG3_EXT_REFREC_SHIFT = (31 - 15);
[all …]
/openbmc/linux/drivers/net/ipa/reg/
H A Dipa_reg-v3.1.c1 // SPDX-License-Identifier: GPL-2.0
11 [COMP_CFG_ENABLE] = BIT(0),
16 /* Bits 5-31 reserved */
19 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
22 [CLKON_RX] = BIT(0),
39 /* Bits 17-31 reserved */
42 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
45 [ROUTE_DIS] = BIT(0),
50 /* Bits 22-23 reserved */
52 /* Bits 25-31 reserved */
[all …]
H A Dipa_reg-v3.5.1.c1 // SPDX-License-Identifier: GPL-2.0
11 [COMP_CFG_ENABLE] = BIT(0),
16 /* Bits 5-31 reserved */
19 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
22 [CLKON_RX] = BIT(0),
44 /* Bits 22-31 reserved */
47 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
50 [ROUTE_DIS] = BIT(0),
55 /* Bits 22-23 reserved */
57 /* Bits 25-31 reserved */
[all …]
H A Dipa_reg-v5.0.c1 // SPDX-License-Identifier: GPL-2.0
11 [MAX_PIPES] = GENMASK(7, 0),
14 [PROD_LOWEST] = GENMASK(31, 24),
17 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
20 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
43 /* Bits 28-29 reserved */
45 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
48 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000002c);
51 [CLKON_RX] = BIT(0),
82 [DRBIP] = BIT(31),
[all …]
H A Dipa_reg-v4.2.c1 // SPDX-License-Identifier: GPL-2.0
11 /* Bit 0 reserved */
29 /* Bits 21-31 reserved */
32 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
35 [CLKON_RX] = BIT(0),
65 /* Bits 30-31 reserved */
68 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
71 [ROUTE_DIS] = BIT(0),
76 /* Bits 22-23 reserved */
78 /* Bits 25-31 reserved */
[all …]
H A Dipa_reg-v4.11.c1 // SPDX-License-Identifier: GPL-2.0
11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
34 /* Bits 24-29 reserved */
36 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
39 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
42 [CLKON_RX] = BIT(0),
73 [DRBIP] = BIT(31),
76 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
79 [ROUTE_DIS] = BIT(0),
84 /* Bits 22-23 reserved */
[all …]
/openbmc/qemu/hw/nvram/
H A Dxlnx-zynqmp-efuse.c29 #include "hw/nvram/xlnx-zynqmp-efuse.h"
34 #include "hw/qdev-properties.h"
37 #define ZYNQMP_EFUSE_ERR_DEBUG 0
40 REG32(WR_LOCK, 0x0)
41 FIELD(WR_LOCK, LOCK, 0, 16)
42 REG32(CFG, 0x4)
46 FIELD(CFG, EFUSE_CLK_SEL, 0, 1)
47 REG32(STATUS, 0x8)
54 FIELD(STATUS, EFUSE_0_TBIT, 0, 1)
55 REG32(EFUSE_PGM_ADDR, 0xc)
[all …]
/openbmc/linux/arch/arc/include/asm/
H A Dbitops.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
23 * This is a pure count, so (1-32) or (0-31) doesn't apply
24 * It could be 0 to 32, based on num of 0's in there
25 * clz(0x8000_0000) = 0, clz(0xFFFF_FFFF)=0, clz(0) = 32, clz(1) = 31
32 " norm.f %0, %1 \n" in clz()
33 " mov.n %0, 0 \n" in clz()
34 " add.p %0, %0, 1 \n" in clz()
47 return 0; in constant_fls()
48 if (!(x & 0xffff0000u)) { in constant_fls()
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_LENGTH GENMASK(15, 0)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
22 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
24 #define MT_RXD1_FIRST_AMSDU_FRAME GENMASK(1, 0)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
39 #define MT_RXD1_NORMAL_HTC_VLD BIT(0)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
59 #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
61 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
[all …]

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