Lines Matching +full:0 +full:- +full:31
1 // SPDX-License-Identifier: GPL-2.0
11 [COMP_CFG_ENABLE] = BIT(0),
16 /* Bits 5-31 reserved */
19 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
22 [CLKON_RX] = BIT(0),
44 /* Bits 22-31 reserved */
47 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
50 [ROUTE_DIS] = BIT(0),
55 /* Bits 22-23 reserved */
57 /* Bits 25-31 reserved */
60 REG_FIELDS(ROUTE, route, 0x00000048);
63 [MEM_SIZE] = GENMASK(15, 0),
64 [MEM_BADDR] = GENMASK(31, 16),
67 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
70 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
72 /* Bits 8-31 reserved */
75 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
78 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
82 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
85 [IPV6_ROUTER_HASH] = BIT(0),
86 /* Bits 1-3 reserved */
88 /* Bits 5-7 reserved */
90 /* Bits 9-11 reserved */
92 /* Bits 13-31 reserved */
95 REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c);
98 [IPV6_ROUTER_HASH] = BIT(0),
99 /* Bits 1-3 reserved */
101 /* Bits 5-7 reserved */
103 /* Bits 9-11 reserved */
105 /* Bits 13-31 reserved */
108 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090);
110 /* Valid bits defined by ipa->available */
111 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004);
113 REG(IPA_BCR, ipa_bcr, 0x000001d0);
116 [IPA_BASE_ADDR] = GENMASK(16, 0),
117 /* Bits 17-31 reserved */
121 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
123 /* Valid bits defined by ipa->available */
124 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
127 /* Bits 0-3 reserved */
129 /* Bits 5-31 reserved */
132 REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
135 [TX0_PREFETCH_DISABLE] = BIT(0),
138 /* Bits 5-31 reserved */
141 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
144 [MAX_PIPES] = GENMASK(3, 0),
145 /* Bits 4-7 reserved */
147 /* Bits 13-15 reserved */
149 /* Bits 21-23 reserved */
151 /* Bits 28-31 reserved */
154 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
157 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
159 /* Bits 17-31 reserved */
162 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220);
165 [X_MIN_LIM] = GENMASK(5, 0),
166 /* Bits 6-7 reserved */
168 /* Bits 14-15 reserved */
170 /* Bits 22-23 reserved */
172 /* Bits 30-31 reserved */
176 0x00000400, 0x0020);
179 [X_MIN_LIM] = GENMASK(5, 0),
180 /* Bits 6-7 reserved */
182 /* Bits 14-15 reserved */
184 /* Bits 22-23 reserved */
186 /* Bits 30-31 reserved */
190 0x00000404, 0x0020);
193 [X_MIN_LIM] = GENMASK(5, 0),
194 /* Bits 6-7 reserved */
196 /* Bits 14-15 reserved */
198 /* Bits 22-23 reserved */
200 /* Bits 30-31 reserved */
204 0x00000500, 0x0020);
207 [X_MIN_LIM] = GENMASK(5, 0),
208 /* Bits 6-7 reserved */
210 /* Bits 14-15 reserved */
212 /* Bits 22-23 reserved */
214 /* Bits 30-31 reserved */
218 0x00000504, 0x0020);
221 [ENDP_SUSPEND] = BIT(0),
223 /* Bits 2-31 reserved */
226 REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
229 [FRAG_OFFLOAD_EN] = BIT(0),
234 /* Bits 9-31 reserved */
237 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
240 [NAT_EN] = GENMASK(1, 0),
241 /* Bits 2-31 reserved */
244 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
247 [HDR_LEN] = GENMASK(5, 0),
256 /* Bits 29-31 reserved */
259 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
262 [HDR_ENDIANNESS] = BIT(0),
268 /* Bits 14-31 reserved */
271 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
274 0x00000818, 0x0070);
277 [ENDP_MODE] = GENMASK(2, 0),
280 /* Bits 9-11 reserved */
285 /* Bit 31 reserved */
288 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
291 [AGGR_EN] = GENMASK(1, 0),
300 /* Bits 25-31 reserved */
303 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
306 [HOL_BLOCK_EN] = BIT(0),
307 /* Bits 1-31 reserved */
311 0x0000082c, 0x0070);
315 [TIMER_BASE_VALUE] = GENMASK(31, 0),
319 0x00000830, 0x0070);
322 [DEAGGR_HDR_LEN] = GENMASK(5, 0),
328 [MAX_PACKET_LEN] = GENMASK(31, 16),
331 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
334 [ENDP_RSRC_GRP] = GENMASK(1, 0),
335 /* Bits 2-31 reserved */
338 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
341 [SEQ_TYPE] = GENMASK(7, 0),
343 /* Bits 16-31 reserved */
346 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
349 [STATUS_EN] = BIT(0),
351 /* Bits 6-7 reserved */
353 /* Bits 9-31 reserved */
356 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
359 [FILTER_HASH_MSK_SRC_ID] = BIT(0),
366 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0),
367 /* Bits 7-15 reserved */
376 /* Bits 23-31 reserved */
380 0x0000085c, 0x0070);
383 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
386 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
389 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
392 [UC_INTR] = BIT(0),
393 /* Bits 1-31 reserved */
396 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
398 /* Valid bits defined by ipa->available */
400 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
402 /* Valid bits defined by ipa->available */
404 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
406 /* Valid bits defined by ipa->available */
408 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);