Lines Matching +full:0 +full:- +full:31
1 // SPDX-License-Identifier: GPL-2.0
11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
34 /* Bits 24-29 reserved */
36 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
39 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
42 [CLKON_RX] = BIT(0),
73 [DRBIP] = BIT(31),
76 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
79 [ROUTE_DIS] = BIT(0),
84 /* Bits 22-23 reserved */
86 /* Bits 25-31 reserved */
89 REG_FIELDS(ROUTE, route, 0x00000048);
92 [MEM_SIZE] = GENMASK(15, 0),
93 [MEM_BADDR] = GENMASK(31, 16),
96 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
99 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
101 /* Bits 8-31 reserved */
104 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
107 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
109 /* Bits 8-15 reserved */
111 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
114 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
117 [IPV6_ROUTER_HASH] = BIT(0),
118 /* Bits 1-3 reserved */
120 /* Bits 5-7 reserved */
122 /* Bits 9-11 reserved */
124 /* Bits 13-31 reserved */
127 REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
130 [IPV6_ROUTER_HASH] = BIT(0),
131 /* Bits 1-3 reserved */
133 /* Bits 5-7 reserved */
135 /* Bits 9-11 reserved */
137 /* Bits 13-31 reserved */
140 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
142 /* Valid bits defined by ipa->available */
143 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
146 [IPA_BASE_ADDR] = GENMASK(17, 0),
147 /* Bits 18-31 reserved */
151 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
153 /* Valid bits defined by ipa->available */
154 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
157 /* Bits 0-1 reserved */
166 /* Bits 19-31 reserved */
169 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
172 [MAX_PIPES] = GENMASK(4, 0),
173 /* Bits 5-7 reserved */
175 /* Bits 13-15 reserved */
177 /* Bits 21-23 reserved */
179 /* Bits 28-31 reserved */
182 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
185 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
187 /* Bits 17-31 reserved */
190 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
193 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
194 /* Bits 5-6 reserved */
197 /* Bits 13-15 reserved */
199 /* Bits 21-31 reserved */
202 REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
205 [DIV_VALUE] = GENMASK(8, 0),
206 /* Bits 9-30 reserved */
207 [DIV_ENABLE] = BIT(31),
210 REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
213 [PULSE_GRAN_0] = GENMASK(2, 0),
216 /* Bits 9-31 reserved */
219 REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
222 [X_MIN_LIM] = GENMASK(5, 0),
223 /* Bits 6-7 reserved */
225 /* Bits 14-15 reserved */
227 /* Bits 22-23 reserved */
229 /* Bits 30-31 reserved */
233 0x00000400, 0x0020);
236 [X_MIN_LIM] = GENMASK(5, 0),
237 /* Bits 6-7 reserved */
239 /* Bits 14-15 reserved */
241 /* Bits 22-23 reserved */
243 /* Bits 30-31 reserved */
247 0x00000404, 0x0020);
250 [X_MIN_LIM] = GENMASK(5, 0),
251 /* Bits 6-7 reserved */
253 /* Bits 14-15 reserved */
255 /* Bits 22-23 reserved */
257 /* Bits 30-31 reserved */
261 0x00000500, 0x0020);
264 [X_MIN_LIM] = GENMASK(5, 0),
265 /* Bits 6-7 reserved */
267 /* Bits 14-15 reserved */
269 /* Bits 22-23 reserved */
271 /* Bits 30-31 reserved */
275 0x00000504, 0x0020);
278 [FRAG_OFFLOAD_EN] = BIT(0),
283 /* Bits 9-31 reserved */
286 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
289 [NAT_EN] = GENMASK(1, 0),
290 /* Bits 2-31 reserved */
293 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
296 [HDR_LEN] = GENMASK(5, 0),
305 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
308 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
311 [HDR_ENDIANNESS] = BIT(0),
317 /* Bits 14-15 reserved */
321 /* Bits 22-31 reserved */
324 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
327 0x00000818, 0x0070);
330 [ENDP_MODE] = GENMASK(2, 0),
333 /* Bits 9-11 reserved */
338 /* Bit 31 reserved */
341 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
344 [AGGR_EN] = GENMASK(1, 0),
355 /* Bits 28-31 reserved */
358 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
361 [HOL_BLOCK_EN] = BIT(0),
362 /* Bits 1-31 reserved */
366 0x0000082c, 0x0070);
369 [TIMER_LIMIT] = GENMASK(4, 0),
370 /* Bits 5-7 reserved */
372 /* Bits 9-31 reserved */
376 0x00000830, 0x0070);
379 [DEAGGR_HDR_LEN] = GENMASK(5, 0),
385 [MAX_PACKET_LEN] = GENMASK(31, 16),
388 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
391 [ENDP_RSRC_GRP] = GENMASK(1, 0),
392 /* Bits 2-31 reserved */
395 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
398 [SEQ_TYPE] = GENMASK(7, 0),
399 /* Bits 8-31 reserved */
402 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
405 [STATUS_EN] = BIT(0),
407 /* Bits 6-8 reserved */
409 /* Bits 10-31 reserved */
412 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
415 [FILTER_HASH_MSK_SRC_ID] = BIT(0),
422 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0),
423 /* Bits 7-15 reserved */
432 /* Bits 23-31 reserved */
436 0x0000085c, 0x0070);
439 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP);
442 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP);
445 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP);
448 [UC_INTR] = BIT(0),
449 /* Bits 1-31 reserved */
452 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP);
454 /* Valid bits defined by ipa->available */
456 0x00004030 + 0x1000 * GSI_EE_AP, 0x0004);
458 /* Valid bits defined by ipa->available */
460 0x00004034 + 0x1000 * GSI_EE_AP, 0x0004);
462 /* Valid bits defined by ipa->available */
464 0x00004038 + 0x1000 * GSI_EE_AP, 0x0004);