Lines Matching +full:0 +full:- +full:31
1 // SPDX-License-Identifier: GPL-2.0
11 [MAX_PIPES] = GENMASK(7, 0),
14 [PROD_LOWEST] = GENMASK(31, 24),
17 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
20 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
43 /* Bits 28-29 reserved */
45 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
48 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000002c);
51 [CLKON_RX] = BIT(0),
82 [DRBIP] = BIT(31),
85 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000034);
88 [ROUTE_DEF_PIPE] = GENMASK(7, 0),
94 /* Bits 29-31 reserved */
97 REG_FIELDS(ROUTE, route, 0x00000038);
100 [MEM_SIZE] = GENMASK(15, 0),
101 [MEM_BADDR] = GENMASK(31, 16),
104 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000040);
107 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
109 /* Bits 8-31 reserved */
112 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000054);
115 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
117 /* Bits 8-15 reserved */
119 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
122 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000058);
124 /* Valid bits defined by ipa->available */
126 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x00000100, 0x0004);
129 [ROUTER_CACHE] = BIT(0),
130 /* Bits 1-3 reserved */
132 /* Bits 5-31 reserved */
135 REG_FIELDS(FILT_ROUT_CACHE_FLUSH, filt_rout_cache_flush, 0x0000404);
138 [IPA_BASE_ADDR] = GENMASK(17, 0),
139 /* Bits 18-31 reserved */
143 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x00000478);
146 /* Bits 0-1 reserved */
157 /* Bits 21-31 reserved */
160 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x00000488);
163 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
165 /* Bits 17-31 reserved */
168 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x000004a8);
171 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
172 /* Bits 5-6 reserved */
175 /* Bits 13-15 reserved */
177 /* Bits 21-31 reserved */
180 REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x000004ac);
183 [DIV_VALUE] = GENMASK(8, 0),
184 /* Bits 9-30 reserved */
185 [DIV_ENABLE] = BIT(31),
188 REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x000004b0);
191 [PULSE_GRAN_0] = GENMASK(2, 0),
195 /* Bits 12-31 reserved */
198 REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x000004b4);
201 [X_MIN_LIM] = GENMASK(5, 0),
202 /* Bits 6-7 reserved */
204 /* Bits 14-15 reserved */
206 /* Bits 22-23 reserved */
208 /* Bits 30-31 reserved */
212 0x00000500, 0x0020);
215 [X_MIN_LIM] = GENMASK(5, 0),
216 /* Bits 6-7 reserved */
218 /* Bits 14-15 reserved */
220 /* Bits 22-23 reserved */
222 /* Bits 30-31 reserved */
226 0x00000504, 0x0020);
229 [X_MIN_LIM] = GENMASK(5, 0),
230 /* Bits 6-7 reserved */
232 /* Bits 14-15 reserved */
234 /* Bits 22-23 reserved */
236 /* Bits 30-31 reserved */
240 0x00000508, 0x0020);
243 [X_MIN_LIM] = GENMASK(5, 0),
244 /* Bits 6-7 reserved */
246 /* Bits 14-15 reserved */
248 /* Bits 22-23 reserved */
250 /* Bits 30-31 reserved */
254 0x0000050c, 0x0020);
257 [X_MIN_LIM] = GENMASK(5, 0),
258 /* Bits 6-7 reserved */
260 /* Bits 14-15 reserved */
262 /* Bits 22-23 reserved */
264 /* Bits 30-31 reserved */
268 0x00000600, 0x0020);
271 [X_MIN_LIM] = GENMASK(5, 0),
272 /* Bits 6-7 reserved */
274 /* Bits 14-15 reserved */
276 /* Bits 22-23 reserved */
278 /* Bits 30-31 reserved */
282 0x00000604, 0x0020);
285 [X_MIN_LIM] = GENMASK(5, 0),
286 /* Bits 6-7 reserved */
288 /* Bits 14-15 reserved */
290 /* Bits 22-23 reserved */
292 /* Bits 30-31 reserved */
296 0x00000608, 0x0020);
299 [X_MIN_LIM] = GENMASK(5, 0),
300 /* Bits 6-7 reserved */
302 /* Bits 14-15 reserved */
304 /* Bits 22-23 reserved */
306 /* Bits 30-31 reserved */
310 0x0000060c, 0x0020);
312 /* Valid bits defined by ipa->available */
314 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000006b0, 0x0004);
317 [FRAG_OFFLOAD_EN] = BIT(0),
322 /* Bits 9-31 reserved */
325 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00001008, 0x0080);
328 [NAT_EN] = GENMASK(1, 0),
329 /* Bits 2-31 reserved */
332 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000100c, 0x0080);
335 [HDR_LEN] = GENMASK(5, 0),
344 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
347 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00001010, 0x0080);
350 [HDR_ENDIANNESS] = BIT(0),
356 /* Bits 14-15 reserved */
362 [HDR_BYTES_TO_REMOVE] = GENMASK(31, 24),
365 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00001014, 0x0080);
368 0x00001018, 0x0080);
371 [ENDP_MODE] = GENMASK(2, 0),
378 /* Bit 31 reserved */
381 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00001020, 0x0080);
384 [AGGR_EN] = GENMASK(1, 0),
395 /* Bits 28-31 reserved */
398 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00001024, 0x0080);
401 [HOL_BLOCK_EN] = BIT(0),
402 /* Bits 1-31 reserved */
406 0x0000102c, 0x0080);
409 [TIMER_LIMIT] = GENMASK(4, 0),
410 /* Bits 5-7 reserved */
412 /* Bits 10-31 reserved */
416 0x00001030, 0x0080);
419 [DEAGGR_HDR_LEN] = GENMASK(5, 0),
425 [MAX_PACKET_LEN] = GENMASK(31, 16),
428 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00001034, 0x0080);
431 [ENDP_RSRC_GRP] = GENMASK(2, 0),
432 /* Bits 3-31 reserved */
435 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00001038, 0x0080);
438 [SEQ_TYPE] = GENMASK(7, 0),
439 /* Bits 8-31 reserved */
442 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000103c, 0x0080);
445 [STATUS_EN] = BIT(0),
448 /* Bits 10-31 reserved */
451 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00001040, 0x0080);
454 [CACHE_MSK_SRC_ID] = BIT(0),
461 /* Bits 7-31 reserved */
465 0x0000105c, 0x0080);
468 [CACHE_MSK_SRC_ID] = BIT(0),
475 /* Bits 7-31 reserved */
479 0x00001070, 0x0080);
482 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x0000c008 + 0x1000 * GSI_EE_AP);
485 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000c00c + 0x1000 * GSI_EE_AP);
488 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x0000c010 + 0x1000 * GSI_EE_AP);
491 [UC_INTR] = BIT(0),
492 /* Bits 1-31 reserved */
495 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000c01c + 0x1000 * GSI_EE_AP);
497 /* Valid bits defined by ipa->available */
500 0x0000c030 + 0x1000 * GSI_EE_AP, 0x0004);
502 /* Valid bits defined by ipa->available */
505 0x0000c050 + 0x1000 * GSI_EE_AP, 0x0004);
507 /* Valid bits defined by ipa->available */
510 0x0000c070 + 0x1000 * GSI_EE_AP, 0x0004);