Lines Matching +full:0 +full:- +full:31
29 #include "hw/nvram/xlnx-zynqmp-efuse.h"
34 #include "hw/qdev-properties.h"
37 #define ZYNQMP_EFUSE_ERR_DEBUG 0
40 REG32(WR_LOCK, 0x0)
41 FIELD(WR_LOCK, LOCK, 0, 16)
42 REG32(CFG, 0x4)
46 FIELD(CFG, EFUSE_CLK_SEL, 0, 1)
47 REG32(STATUS, 0x8)
54 FIELD(STATUS, EFUSE_0_TBIT, 0, 1)
55 REG32(EFUSE_PGM_ADDR, 0xc)
58 FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5)
59 REG32(EFUSE_RD_ADDR, 0x10)
62 REG32(EFUSE_RD_DATA, 0x14)
63 REG32(TPGM, 0x18)
64 FIELD(TPGM, VALUE, 0, 16)
65 REG32(TRD, 0x1c)
66 FIELD(TRD, VALUE, 0, 8)
67 REG32(TSU_H_PS, 0x20)
68 FIELD(TSU_H_PS, VALUE, 0, 8)
69 REG32(TSU_H_PS_CS, 0x24)
70 FIELD(TSU_H_PS_CS, VALUE, 0, 8)
71 REG32(TSU_H_CS, 0x2c)
72 FIELD(TSU_H_CS, VALUE, 0, 4)
73 REG32(EFUSE_ISR, 0x30)
74 FIELD(EFUSE_ISR, APB_SLVERR, 31, 1)
79 FIELD(EFUSE_ISR, PGM_DONE, 0, 1)
80 REG32(EFUSE_IMR, 0x34)
81 FIELD(EFUSE_IMR, APB_SLVERR, 31, 1)
86 FIELD(EFUSE_IMR, PGM_DONE, 0, 1)
87 REG32(EFUSE_IER, 0x38)
88 FIELD(EFUSE_IER, APB_SLVERR, 31, 1)
93 FIELD(EFUSE_IER, PGM_DONE, 0, 1)
94 REG32(EFUSE_IDR, 0x3c)
95 FIELD(EFUSE_IDR, APB_SLVERR, 31, 1)
100 FIELD(EFUSE_IDR, PGM_DONE, 0, 1)
101 REG32(EFUSE_CACHE_LOAD, 0x40)
102 FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1)
103 REG32(EFUSE_PGM_LOCK, 0x44)
104 FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1)
105 REG32(EFUSE_AES_CRC, 0x48)
106 REG32(EFUSE_TBITS_PRGRMG_EN, 0x100)
108 REG32(DNA_0, 0x100c)
109 REG32(DNA_1, 0x1010)
110 REG32(DNA_2, 0x1014)
111 REG32(IPDISABLE, 0x1018)
117 FIELD(IPDISABLE, APU0_DIS, 0, 1)
118 REG32(SYSOSC_CTRL, 0x101c)
119 FIELD(SYSOSC_CTRL, SYSOSC_EN, 0, 1)
120 REG32(USER_0, 0x1020)
121 REG32(USER_1, 0x1024)
122 REG32(USER_2, 0x1028)
123 REG32(USER_3, 0x102c)
124 REG32(USER_4, 0x1030)
125 REG32(USER_5, 0x1034)
126 REG32(USER_6, 0x1038)
127 REG32(USER_7, 0x103c)
128 REG32(MISC_USER_CTRL, 0x1040)
139 FIELD(MISC_USER_CTRL, USR_WRLK_0, 0, 1)
140 REG32(ROM_RSVD, 0x1044)
141 FIELD(ROM_RSVD, PBR_BOOT_ERROR, 0, 3)
142 REG32(PUF_CHASH, 0x1050)
143 REG32(PUF_MISC, 0x1054)
144 FIELD(PUF_MISC, REGISTER_DIS, 31, 1)
152 FIELD(PUF_MISC, AUX, 0, 24)
153 REG32(SEC_CTRL, 0x1058)
169 FIELD(SEC_CTRL, AES_RDLK, 0, 1)
170 REG32(SPK_ID, 0x105c)
171 REG32(PPK0_0, 0x10a0)
172 REG32(PPK0_1, 0x10a4)
173 REG32(PPK0_2, 0x10a8)
174 REG32(PPK0_3, 0x10ac)
175 REG32(PPK0_4, 0x10b0)
176 REG32(PPK0_5, 0x10b4)
177 REG32(PPK0_6, 0x10b8)
178 REG32(PPK0_7, 0x10bc)
179 REG32(PPK0_8, 0x10c0)
180 REG32(PPK0_9, 0x10c4)
181 REG32(PPK0_10, 0x10c8)
182 REG32(PPK0_11, 0x10cc)
183 REG32(PPK1_0, 0x10d0)
184 REG32(PPK1_1, 0x10d4)
185 REG32(PPK1_2, 0x10d8)
186 REG32(PPK1_3, 0x10dc)
187 REG32(PPK1_4, 0x10e0)
188 REG32(PPK1_5, 0x10e4)
189 REG32(PPK1_6, 0x10e8)
190 REG32(PPK1_7, 0x10ec)
191 REG32(PPK1_8, 0x10f0)
192 REG32(PPK1_9, 0x10f4)
193 REG32(PPK1_10, 0x10f8)
194 REG32(PPK1_11, 0x10fc)
203 * ZynqMP: UG1085 (v2.1) August 21, 2019, p.277, Table 12-13
205 #define EFUSE_AES_RDLK BIT_POS(22, 0)
223 #define EFUSE_PPK1_INVLD_1 BIT_POS(22, 31)
226 #define EFUSE_TRIM_START BIT_POS(1, 0)
228 #define EFUSE_DNA_START BIT_POS(3, 0)
229 #define EFUSE_DNA_END BIT_POS(5, 31)
230 #define EFUSE_AES_START BIT_POS(24, 0)
231 #define EFUSE_AES_END BIT_POS(31, 31)
232 #define EFUSE_ROM_START BIT_POS(17, 0)
233 #define EFUSE_ROM_END BIT_POS(17, 31)
234 #define EFUSE_IPDIS_START BIT_POS(6, 0)
235 #define EFUSE_IPDIS_END BIT_POS(6, 31)
236 #define EFUSE_USER_START BIT_POS(8, 0)
237 #define EFUSE_USER_END BIT_POS(15, 31)
238 #define EFUSE_BISR_START BIT_POS(32, 0)
239 #define EFUSE_BISR_END BIT_POS(39, 31)
241 #define EFUSE_USER_CTRL_START BIT_POS(16, 0)
243 #define EFUSE_USER_CTRL_MASK ((uint32_t)MAKE_64BIT_MASK(0, 17))
245 #define EFUSE_PUF_CHASH_START BIT_POS(20, 0)
246 #define EFUSE_PUF_CHASH_END BIT_POS(20, 31)
247 #define EFUSE_PUF_MISC_START BIT_POS(21, 0)
248 #define EFUSE_PUF_MISC_END BIT_POS(21, 31)
251 #define EFUSE_SPK_START BIT_POS(23, 0)
252 #define EFUSE_SPK_END BIT_POS(23, 31)
254 #define EFUSE_PPK0_START BIT_POS(40, 0)
255 #define EFUSE_PPK0_END BIT_POS(51, 31)
256 #define EFUSE_PPK1_START BIT_POS(52, 0)
257 #define EFUSE_PPK1_END BIT_POS(63, 31)
260 ARRAY_FIELD_DP32((s)->regs, reg, field, \
261 (xlnx_efuse_get_row((s->efuse), EFUSE_ ## field) \
265 ARRAY_FIELD_DP32((s)->regs, reg, field, xlnx_efuse_get_bit((s->efuse), \
268 #define FBIT_UNKNOWN (~0)
270 QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxZynqMPEFuse *)0)->regs));
274 unsigned int check = xlnx_efuse_tbits_check(s->efuse); in update_tbit_status()
275 uint32_t val = s->regs[R_STATUS]; in update_tbit_status()
277 val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0))); in update_tbit_status()
281 s->regs[R_STATUS] = val; in update_tbit_status()
289 uint32_t *u32 = &s->regs[r_start]; in cache_sync_u32()
290 unsigned int fbit, wbits = 0, u32_off = 0; in cache_sync_u32()
302 wbits = 0; in cache_sync_u32()
304 u32[u32_off] |= xlnx_efuse_get_bit(s->efuse, fbit) << wbits; in cache_sync_u32()
336 s->regs[R_MISC_USER_CTRL] = xlnx_efuse_get_row(s->efuse, in zynqmp_efuse_sync_cache()
339 s->regs[R_PUF_CHASH] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_CHASH_START); in zynqmp_efuse_sync_cache()
340 s->regs[R_PUF_MISC] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_MISC_START); in zynqmp_efuse_sync_cache()
358 bool pending = s->regs[R_EFUSE_ISR] & s->regs[R_EFUSE_IMR]; in zynqmp_efuse_update_irq()
359 qemu_set_irq(s->irq, pending); in zynqmp_efuse_update_irq()
364 XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); in zynqmp_efuse_isr_postw()
370 XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); in zynqmp_efuse_ier_prew()
373 s->regs[R_EFUSE_IMR] |= val; in zynqmp_efuse_ier_prew()
375 return 0; in zynqmp_efuse_ier_prew()
380 XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); in zynqmp_efuse_idr_prew()
383 s->regs[R_EFUSE_IMR] &= ~val; in zynqmp_efuse_idr_prew()
385 return 0; in zynqmp_efuse_idr_prew()
390 XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); in zynqmp_efuse_pgm_addr_postw()
398 case 0: in zynqmp_efuse_pgm_addr_postw()
401 bit = FIELD_DP32(bit, EFUSE_PGM_ADDR, EFUSE, page - 1); in zynqmp_efuse_pgm_addr_postw()
402 puf_prot = xlnx_efuse_get_bit(s->efuse, EFUSE_PUF_SYN_WRLK); in zynqmp_efuse_pgm_addr_postw()
409 if (ARRAY_FIELD_EX32(s->regs, WR_LOCK, LOCK)) { in zynqmp_efuse_pgm_addr_postw()
410 errmsg = "Array write-locked"; in zynqmp_efuse_pgm_addr_postw()
414 if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) { in zynqmp_efuse_pgm_addr_postw()
415 errmsg = "Array pgm-disabled"; in zynqmp_efuse_pgm_addr_postw()
420 errmsg = "PUF_HD-store write-locked"; in zynqmp_efuse_pgm_addr_postw()
424 if (ARRAY_FIELD_EX32(s->regs, SEC_CTRL, AES_WRLK) in zynqmp_efuse_pgm_addr_postw()
426 errmsg = "AES key-store Write-locked"; in zynqmp_efuse_pgm_addr_postw()
430 if (!xlnx_efuse_set_bit(s->efuse, bit)) { in zynqmp_efuse_pgm_addr_postw()
436 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 0); in zynqmp_efuse_pgm_addr_postw()
440 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1); in zynqmp_efuse_pgm_addr_postw()
442 "%s - eFuse write error: %s; addr=0x%x\n", in zynqmp_efuse_pgm_addr_postw()
446 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1); in zynqmp_efuse_pgm_addr_postw()
452 XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); in zynqmp_efuse_rd_addr_postw()
457 * 1/ XilSKey - XilSKey_ZynqMp_EfusePs_ReadRow() in zynqmp_efuse_rd_addr_postw()
458 * 2/ UG1085, v2.0, table 12-13 in zynqmp_efuse_rd_addr_postw()
463 ((uint32_t)MAKE_64BIT_MASK((L_), (1 + (H_) - (L_)))) in zynqmp_efuse_rd_addr_postw()
466 /* XilSKey - XSK_ZYNQMP_EFUSEPS_TBITS_ROW */ in zynqmp_efuse_rd_addr_postw()
467 [0] = COL_MASK(28, 31), in zynqmp_efuse_rd_addr_postw()
469 /* XilSKey - XSK_ZYNQMP_EFUSEPS_USR{0:7}_FUSE_ROW */ in zynqmp_efuse_rd_addr_postw()
470 [8] = COL_MASK(0, 31), [9] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
471 [10] = COL_MASK(0, 31), [11] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
472 [12] = COL_MASK(0, 31), [13] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
473 [14] = COL_MASK(0, 31), [15] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
475 /* XilSKey - XSK_ZYNQMP_EFUSEPS_MISC_USR_CTRL_ROW */ in zynqmp_efuse_rd_addr_postw()
476 [16] = COL_MASK(0, 7) | COL_MASK(10, 16), in zynqmp_efuse_rd_addr_postw()
478 /* XilSKey - XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_ROW */ in zynqmp_efuse_rd_addr_postw()
479 [17] = COL_MASK(0, 2), in zynqmp_efuse_rd_addr_postw()
481 /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_CHASH_ROW */ in zynqmp_efuse_rd_addr_postw()
482 [20] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
484 /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_AUX_ROW */ in zynqmp_efuse_rd_addr_postw()
485 [21] = COL_MASK(0, 23) | COL_MASK(29, 31), in zynqmp_efuse_rd_addr_postw()
487 /* XilSKey - XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW */ in zynqmp_efuse_rd_addr_postw()
488 [22] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
490 /* XilSKey - XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW */ in zynqmp_efuse_rd_addr_postw()
491 [23] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
493 /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW */ in zynqmp_efuse_rd_addr_postw()
494 [40] = COL_MASK(0, 31), [41] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
495 [42] = COL_MASK(0, 31), [43] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
496 [44] = COL_MASK(0, 31), [45] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
497 [46] = COL_MASK(0, 31), [47] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
498 [48] = COL_MASK(0, 31), [49] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
499 [50] = COL_MASK(0, 31), [51] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
501 /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW */ in zynqmp_efuse_rd_addr_postw()
502 [52] = COL_MASK(0, 31), [53] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
503 [54] = COL_MASK(0, 31), [55] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
504 [56] = COL_MASK(0, 31), [57] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
505 [58] = COL_MASK(0, 31), [59] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
506 [60] = COL_MASK(0, 31), [61] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
507 [62] = COL_MASK(0, 31), [63] = COL_MASK(0, 31), in zynqmp_efuse_rd_addr_postw()
510 uint32_t col_mask = COL_MASK(0, 31); in zynqmp_efuse_rd_addr_postw()
513 uint32_t efuse_idx = s->regs[R_EFUSE_RD_ADDR]; in zynqmp_efuse_rd_addr_postw()
518 case 0: /* Various */ in zynqmp_efuse_rd_addr_postw()
530 val64 = FIELD_DP32(efuse_idx, EFUSE_RD_ADDR, EFUSE, efuse_ary - 1); in zynqmp_efuse_rd_addr_postw()
536 s->regs[R_EFUSE_RD_DATA] = xlnx_efuse_get_row(s->efuse, val64) & col_mask; in zynqmp_efuse_rd_addr_postw()
538 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 0); in zynqmp_efuse_rd_addr_postw()
539 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1); in zynqmp_efuse_rd_addr_postw()
549 s->regs[R_EFUSE_RD_DATA] = 0; in zynqmp_efuse_rd_addr_postw()
551 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1); in zynqmp_efuse_rd_addr_postw()
552 ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 0); in zynqmp_efuse_rd_addr_postw()
558 XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); in zynqmp_efuse_aes_crc_postw()
561 ok = xlnx_efuse_k256_check(s->efuse, (uint32_t)val64, EFUSE_AES_START); in zynqmp_efuse_aes_crc_postw()
563 ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_PASS, (ok ? 1 : 0)); in zynqmp_efuse_aes_crc_postw()
564 ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_DONE, 1); in zynqmp_efuse_aes_crc_postw()
566 s->regs[R_EFUSE_AES_CRC] = 0; /* crc value is write-only */ in zynqmp_efuse_aes_crc_postw()
572 XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); in zynqmp_efuse_cache_load_prew()
576 ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1); in zynqmp_efuse_cache_load_prew()
580 return 0; in zynqmp_efuse_cache_load_prew()
585 return val == 0xDF0D ? 0 : 1; in zynqmp_efuse_wr_lock_prew()
590 .reset = 0x1,
594 .rsvd = 0x8,
595 .ro = 0xff,
599 .rsvd = 0x1f,
602 .ro = 0xffffffff,
605 .reset = 0x1b,
607 .reset = 0xff,
609 .reset = 0xb,
611 .reset = 0x7,
613 .rsvd = 0x7fffffe0,
614 .w1c = 0x8000001f,
617 .reset = 0x8000001f,
618 .rsvd = 0x7fffffe0,
619 .ro = 0xffffffff,
621 .rsvd = 0x7fffffe0,
624 .rsvd = 0x7fffffe0,
634 .ro = 0xffffffff,
636 .ro = 0xffffffff,
638 .ro = 0xffffffff,
640 .ro = 0xffffffff,
642 .ro = 0xffffffff,
644 .ro = 0xffffffff,
646 .ro = 0xffffffff,
648 .ro = 0xffffffff,
650 .ro = 0xffffffff,
652 .ro = 0xffffffff,
654 .ro = 0xffffffff,
656 .ro = 0xffffffff,
658 .ro = 0xffffffff,
660 .ro = 0xffffffff,
662 .ro = 0xffffffff,
664 .ro = 0xffffffff,
666 .ro = 0xffffffff,
668 .ro = 0xffffffff,
670 .ro = 0xffffffff,
672 .ro = 0xffffffff,
674 .ro = 0xffffffff,
676 .ro = 0xffffffff,
678 .ro = 0xffffffff,
680 .ro = 0xffffffff,
682 .ro = 0xffffffff,
684 .ro = 0xffffffff,
686 .ro = 0xffffffff,
688 .ro = 0xffffffff,
690 .ro = 0xffffffff,
692 .ro = 0xffffffff,
694 .ro = 0xffffffff,
696 .ro = 0xffffffff,
698 .ro = 0xffffffff,
700 .ro = 0xffffffff,
702 .ro = 0xffffffff,
704 .ro = 0xffffffff,
706 .ro = 0xffffffff,
708 .ro = 0xffffffff,
710 .ro = 0xffffffff,
712 .ro = 0xffffffff,
714 .ro = 0xffffffff,
716 .ro = 0xffffffff,
718 .ro = 0xffffffff,
731 dev = reg_array->mem.owner; in zynqmp_efuse_reg_write()
736 if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) { in zynqmp_efuse_reg_write()
759 if (!reg->data || !reg->access) { in zynqmp_efuse_register_reset()
764 switch (reg->access->addr) { in zynqmp_efuse_register_reset()
766 *(uint32_t *)reg->data = reg->access->reset; in zynqmp_efuse_register_reset()
778 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { in zynqmp_efuse_reset_hold()
779 zynqmp_efuse_register_reset(&s->regs_info[i]); in zynqmp_efuse_reset_hold()
783 ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1); in zynqmp_efuse_reset_hold()
791 if (!s->efuse) { in zynqmp_efuse_realize()
794 error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE", in zynqmp_efuse_realize()
799 s->efuse->dev = dev; in zynqmp_efuse_realize()
807 s->reg_array = in zynqmp_efuse_init()
810 s->regs_info, s->regs, in zynqmp_efuse_init()
815 sysbus_init_mmio(sbd, &s->reg_array->mem); in zynqmp_efuse_init()
816 sysbus_init_irq(sbd, &s->irq); in zynqmp_efuse_init()
823 register_finalize_block(s->reg_array); in zynqmp_efuse_finalize()
849 rc->phases.hold = zynqmp_efuse_reset_hold; in zynqmp_efuse_class_init()
850 dc->realize = zynqmp_efuse_realize; in zynqmp_efuse_class_init()
851 dc->vmsd = &vmstate_efuse; in zynqmp_efuse_class_init()