ipa/reg/ipa_reg-v4.2.c

1 // SPDX-License-Identifier: GPL-2.0
11 						/* Bit 0 reserved */
29 						/* Bits 21-31 reserved */
32 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
35 	[CLKON_RX]					= BIT(0),
65 						/* Bits 30-31 reserved */
68 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
71 	[ROUTE_DIS]					= BIT(0),
76 						/* Bits 22-23 reserved */
78 						/* Bits 25-31 reserved */
81 REG_FIELDS(ROUTE, route, 0x00000048);
84 	[MEM_SIZE]					= GENMASK(15, 0),
85 	[MEM_BADDR]					= GENMASK(31, 16),
88 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
91 	[GEN_QMB_0_MAX_WRITES]				= GENMASK(3, 0),
93 						/* Bits 8-31 reserved */
96 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
99 	[GEN_QMB_0_MAX_READS]				= GENMASK(3, 0),
101 						/* Bits 8-15 reserved */
103 	[GEN_QMB_1_MAX_READS_BEATS]			= GENMASK(31, 24),
106 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
109 	[IPV6_ROUTER_HASH]				= BIT(0),
110 						/* Bits 1-3 reserved */
112 						/* Bits 5-7 reserved */
114 						/* Bits 9-11 reserved */
116 						/* Bits 13-31 reserved */
119 REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
122 	[IPV6_ROUTER_HASH]				= BIT(0),
123 						/* Bits 1-3 reserved */
125 						/* Bits 5-7 reserved */
127 						/* Bits 9-11 reserved */
129 						/* Bits 13-31 reserved */
132 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
134 /* Valid bits defined by ipa->available */
135 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
137 REG(IPA_BCR, ipa_bcr, 0x000001d0);
140 	[IPA_BASE_ADDR]					= GENMASK(16, 0),
141 						/* Bits 17-31 reserved */
145 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
147 /* Valid bits defined by ipa->available */
148 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
151 						/* Bits 0-3 reserved */
153 						/* Bits 9-31 reserved */
156 REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
159 						/* Bits 0-1 reserved */
169 						/* Bits 20-31 reserved */
172 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
175 	[MAX_PIPES]					= GENMASK(3, 0),
176 						/* Bits 4-7 reserved */
178 						/* Bits 13-15 reserved */
180 						/* Bits 21-23 reserved */
182 						/* Bits 28-31 reserved */
185 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
188 	[ENTER_IDLE_DEBOUNCE_THRESH]			= GENMASK(15, 0),
190 						/* Bits 17-31 reserved */
193 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
196 	[X_MIN_LIM]					= GENMASK(5, 0),
197 						/* Bits 6-7 reserved */
199 						/* Bits 14-15 reserved */
201 						/* Bits 22-23 reserved */
203 						/* Bits 30-31 reserved */
207 		  0x00000400, 0x0020);
210 	[X_MIN_LIM]					= GENMASK(5, 0),
211 						/* Bits 6-7 reserved */
213 						/* Bits 14-15 reserved */
215 						/* Bits 22-23 reserved */
217 						/* Bits 30-31 reserved */
221 		  0x00000404, 0x0020);
224 	[X_MIN_LIM]					= GENMASK(5, 0),
225 						/* Bits 6-7 reserved */
227 						/* Bits 14-15 reserved */
229 						/* Bits 22-23 reserved */
231 						/* Bits 30-31 reserved */
235 		  0x00000500, 0x0020);
238 	[X_MIN_LIM]					= GENMASK(5, 0),
239 						/* Bits 6-7 reserved */
241 						/* Bits 14-15 reserved */
243 						/* Bits 22-23 reserved */
245 						/* Bits 30-31 reserved */
249 		  0x00000504, 0x0020);
252 	[FRAG_OFFLOAD_EN]				= BIT(0),
257 						/* Bits 9-31 reserved */
260 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
263 	[NAT_EN]					= GENMASK(1, 0),
264 						/* Bits 2-31 reserved */
267 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
270 	[HDR_LEN]					= GENMASK(5, 0),
279 						/* Bits 29-31 reserved */
282 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
285 	[HDR_ENDIANNESS]				= BIT(0),
291 						/* Bits 14-31 reserved */
294 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
297 	   0x00000818, 0x0070);
300 	[ENDP_MODE]					= GENMASK(2, 0),
303 						/* Bits 9-11 reserved */
308 						/* Bit 31 reserved */
311 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
314 	[AGGR_EN]					= GENMASK(1, 0),
323 						/* Bits 25-31 reserved */
326 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
329 	[HOL_BLOCK_EN]					= BIT(0),
330 						/* Bits 1-31 reserved */
334 		  0x0000082c, 0x0070);
337 	[TIMER_BASE_VALUE]				= GENMASK(4, 0),
338 						/* Bits 5-7 reserved */
340 						/* Bits 9-31 reserved */
344 		  0x00000830, 0x0070);
347 	[DEAGGR_HDR_LEN]				= GENMASK(5, 0),
353 	[MAX_PACKET_LEN]				= GENMASK(31, 16),
356 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
359 	[ENDP_RSRC_GRP]					= BIT(0),
360 						/* Bits 1-31 reserved */
363 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
366 	[SEQ_TYPE]					= GENMASK(7, 0),
368 						/* Bits 16-31 reserved */
371 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
374 	[STATUS_EN]					= BIT(0),
376 						/* Bits 6-7 reserved */
379 						/* Bits 10-31 reserved */
382 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
385 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
388 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
391 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
394 	[UC_INTR]					= BIT(0),
395 						/* Bits 1-31 reserved */
398 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
400 /* Valid bits defined by ipa->available */
402 	   0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
404 /* Valid bits defined by ipa->available */
406 	   0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
408 /* Valid bits defined by ipa->available */
410 	   0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);