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/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dhw_data.c1 // SPDX-License-Identifier: GPL-2.0+
32 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
33 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
34 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
35 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
36 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
37 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
38 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
43 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
44 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c1 // SPDX-License-Identifier: GPL-2.0+
36 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
40 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
41 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
42 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
43 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
44 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
45 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
46 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
50 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
[all …]
/openbmc/qemu/include/hw/misc/macio/
H A Dpmu.h25 #define PMU_ADB_POLL_OFF 0x21 /* disable ADB auto-poll */
26 #define PMU_WRITE_NVRAM 0x33 /* write non-volatile RAM */
27 #define PMU_READ_NVRAM 0x3b /* read non-volatile RAM */
28 #define PMU_SET_RTC 0x30 /* set real-time clock */
29 #define PMU_READ_RTC 0x38 /* read real-time clock */
33 #define PMU_PCEJECT 0x4c /* eject PC-card from slot */
41 #define PMU_POWER_EVENTS 0x8f /* Send power-event commands to PMU */
67 #define PMU_INT_PCEJECT 0x04 /* PC-card eject buttons */
72 #define PMU_INT_TICK 0x80 /* 1-second tick interrupt */
85 #define PMU_I2C_MODE_STDSUB 1
[all …]
/openbmc/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
23 #include "pinctrl-tegra.h"
1281 #define PINGROUP_REG_N(r) -1
1284 #define DRV_PINGROUP_N(r) -1
1287 .drv_reg = -1, \
1288 .drv_bank = -1, \
1289 .drvdn_bit = -1, \
1290 .drvup_bit = -1, \
1291 .slwr_bit = -1, \
[all …]
H A Dpinctrl-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "pinctrl-tegra.h"
23 #define TEGRA_PIN_PEX_L0_CLKREQ_N_PA1 _GPIO(1)
177 /* All non-GPIO pins follow */
178 #define NUM_GPIOS (TEGRA_PIN_QSPI_IO3_PEE5 + 1)
181 /* Non-GPIO pins */
183 #define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
1267 #define PINGROUP_REG_A 0x3000 /* bank 1 */
1269 #define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
1270 #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
[all …]
H A Dpinctrl-tegra234.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
16 #include "pinctrl-tegra.h"
1382 #define PINGROUP_REG_N(r) -1
1385 #define DRV_PINGROUP_N(r) -1
1388 .drv_reg = -1, \
1389 .drv_bank = -1, \
1390 .drvdn_bit = -1, \
1391 .drvup_bit = -1, \
1392 .slwr_bit = -1, \
[all …]
/openbmc/linux/fs/nls/
H A Dnls_ucs2_utils.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 000-00f */
26 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 010-01f */
27 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 020-02f */
28 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 030-03f */
29 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 040-04f */
30 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 050-05f */
31 0, -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
32 -32, -32, -32, -32, -32, /* 060-06f */
33 -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
[all …]
/openbmc/linux/arch/x86/kernel/
H A Duprobes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * User-space Probes (UProbes) for x86
5 * Copyright (C) IBM Corporation, 2008-2011
21 /* Post-execution fixups. */
41 #define OPCODE1(insn) ((insn)->opcode.bytes[0])
42 #define OPCODE2(insn) ((insn)->opcode.bytes[1])
43 #define OPCODE3(insn) ((insn)->opcode.bytes[2])
44 #define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value)
54 * Good-instruction tables for 32-bit apps. This is non-const and volatile
59 * 6c-6f - ins,outs. SEGVs if used in userspace
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
62 CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
64 1000, OSC-1, -1, -1, 10, 8, 4};
68 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
69 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
70 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
71 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
72 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
73 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_spec.h1 /* SPDX-License-Identifier: GPL-2.0 */
27 PEX_BUS_MODE_X1 = 1,
55 * Bus speed - one bit per SERDES line:
56 * Low speed (0) High speed (1)
68 {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
69 {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
70 {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
71 {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
72 {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
73 {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dencode_ext.def2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
24 DEF_ENC(V6_extractw, ICLASS_LD" 001 0 000sssss PP0uuuuu --1ddddd") /* coproc insn, returns Rd */
32 DEF_CLASS32(ICLASS_NCJ" 1--- -------- PP------ --------",COPROC_VMEM)
33 DEF_CLASS32(ICLASS_NCJ" 1000 0-0ttttt PPi--iii ---ddddd",BaseOffset_VMEM_Loads)
34 DEF_CLASS32(ICLASS_NCJ" 1000 1-0ttttt PPivviii ---ddddd",BaseOffset_if_Pv_VMEM_Loads)
35 DEF_CLASS32(ICLASS_NCJ" 1000 0-1ttttt PPi--iii --------",BaseOffset_VMEM_Stores1)
36 DEF_CLASS32(ICLASS_NCJ" 1000 1-0ttttt PPi--iii 00------",BaseOffset_VMEM_Stores2)
37 DEF_CLASS32(ICLASS_NCJ" 1000 1-1ttttt PPivviii --------",BaseOffset_if_Pv_VMEM_Stores)
39 DEF_CLASS32(ICLASS_NCJ" 1001 0-0xxxxx PP---iii ---ddddd",PostImm_VMEM_Loads)
40 DEF_CLASS32(ICLASS_NCJ" 1001 1-0xxxxx PP-vviii ---ddddd",PostImm_if_Pv_VMEM_Loads)
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dstv090x_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
31 #define STV090x_WIDTH_OUTSERRS1_HZ_FIELD 1
33 #define STV090x_WIDTH_OUTSERRS2_HZ_FIELD 1
35 #define STV090x_WIDTH_OUTSERRS3_HZ_FIELD 1
37 #define STV090x_WIDTH_OUTPARRS3_HZ_FIELD 1
43 #define STV090x_WIDTH_SPLL_LOCK_FIELD 1
45 #define STV090x_WIDTH_SSTREAM_LCK_3_FIELD 1
47 #define STV090x_WIDTH_SSTREAM_LCK_2_FIELD 1
49 #define STV090x_WIDTH_SSTREAM_LCK_1_FIELD 1
50 #define STV090x_OFFST_SDVBS1_PRF_2_FIELD 1
[all …]
/openbmc/linux/drivers/media/platform/qcom/camss/
H A Dcamss-video.c1 // SPDX-License-Identifier: GPL-2.0
3 * camss-video.c
5 * Qualcomm MSM Camera Subsystem - V4L2 device node
7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 * Copyright (C) 2015-2018 Linaro Ltd.
11 #include <media/media-entity.h>
12 #include <media/v4l2-dev.h>
13 #include <media/v4l2-device.h>
14 #include <media/v4l2-ioctl.h>
15 #include <media/v4l2-mc.h>
[all …]
/openbmc/linux/drivers/usb/gadget/udc/
H A Dfusb300_udc.h1 // SPDX-License-Identifier: GPL-2.0
7 * Author : Yuan-hsin Chen <yhchen@faraday-tech.com>
21 #define FUSB300_OFFSET_EPSET0(n) (0x20 + (n - 1) * 0x30)
22 #define FUSB300_OFFSET_EPSET1(n) (0x24 + (n - 1) * 0x30)
23 #define FUSB300_OFFSET_EPSET2(n) (0x28 + (n - 1) * 0x30)
24 #define FUSB300_OFFSET_EPFFR(n) (0x2c + (n - 1) * 0x30)
25 #define FUSB300_OFFSET_EPSTRID(n) (0x40 + (n - 1) * 0x30)
54 #define FUSB300_OFFSET_EPPRD_W0(n) (0x520 + (n - 1) * 0x10)
55 #define FUSB300_OFFSET_EPPRD_W1(n) (0x524 + (n - 1) * 0x10)
56 #define FUSB300_OFFSET_EPPRD_W2(n) (0x528 + (n - 1) * 0x10)
[all …]
/openbmc/u-boot/board/freescale/b4860qds/
H A Db4860qds_crossbar_con.h1 /* SPDX-License-Identifier: GPL-2.0+ */
15 static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
16 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
18 static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
20 {-1, -1}, {-1, -1} };
22 static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
24 {-1, -1}, {-1, -1} };
26 static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
32 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
35 static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
[all …]
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dcrop.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
2 <!-- SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later -->
6 xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
9 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
25 ….48 8.19,17.01 -46.93,23.31 29.61,-25.515 -38.12,8.505 47.25,-23.31 z m -1559.25,800.73 -8.5,-17.0…
27 inkscape:connector-curvature="0"
28 style="clip-rule:evenodd" /></clipPath><clipPath
31 …-1626 -1,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2…
32 -1,0 0,1 -1,0 0,1 -1,0 0,1 -2,0 0,1 -1,0 0,2 2,0 0,-1 4,0 0,-1 5,0 0,-1 4,0 0,-1 5,0 0,-1 5,0 0,-1 …
34 inkscape:connector-curvature="0"
[all …]
/openbmc/linux/drivers/clk/ingenic/
H A Dx1830-cgu.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
59 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_enable()
60 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_enable()
69 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_disable()
70 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_disable()
78 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_is_enabled()
79 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_is_enabled()
93 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
[all …]
H A Djz4740-cgu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
38 #define PLLCTL_STABLE (1 << 10)
39 #define PLLCTL_BYPASS (1 << 9)
40 #define PLLCTL_ENABLE (1 << 8)
43 #define LCR_SLEEP (1 << 0)
46 #define CLKGR_UDC (1 << 11)
51 0x0, 0x1, -1, 0x3,
55 1, 2, 3, 4, 6, 8, 12, 16, 24, 32,
[all …]
H A Djz4725b-cgu.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
36 0x0, 0x1, -1, 0x3,
40 1, 2, 3, 4, 6, 8,
44 2, 1,
56 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
59 .rate_multiplier = 1,
81 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
83 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
[all …]
/openbmc/linux/drivers/media/v4l2-core/
H A Dv4l2-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
27 * Video4linux 1/2 integration by Justin Schoeman
46 #include <media/v4l2-common.h>
47 #include <media/v4l2-device.h>
48 #include <media/v4l2-ctrls.h>
73 v4l2_ctrl_fill(qctrl->id, &name, &qctrl->type, in v4l2_ctrl_query_fill()
74 &min, &max, &step, &def, &qctrl->flags); in v4l2_ctrl_query_fill()
77 return -EINVAL; in v4l2_ctrl_query_fill()
79 qctrl->minimum = min; in v4l2_ctrl_query_fill()
80 qctrl->maximum = max; in v4l2_ctrl_query_fill()
[all …]
/openbmc/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
13 # v1.1 defined in version 1.1
23 - e GRBG 0
24 - e RGGB 1
[all …]
/openbmc/linux/arch/alpha/kernel/
H A Dsys_sable.c1 // SPDX-License-Identifier: GPL-2.0
9 * Code supporting the Sable, Sable-Gamma, and Lynx systems.
58 * 0-7 (char at 536)
59 * 8-15 (char at 53a)
60 * 16-23 (char at 53c)
65 *------------------------------------------
67 * 1 NCR810 (builtin) 33
70 * 4 PCI slot 1 35
72 * 6 keyboard 1
76 *10 EISA irq 3 -
[all …]
/openbmc/qemu/chardev/
H A Dbaum.c4 * Copyright (c) 2008, 2010-2011, 2016-2017 Samuel Thibault
28 #include "qemu/main-loop.h"
91 #define Y_MAX 1
110 #define TYPE_CHARDEV_BRAILLE "chardev-braille"
135 DO(BRLAPI_DOTS(1, 0, 0, 0, 0, 0, 0, 0), 'a'),
136 DO(BRLAPI_DOTS(1, 1, 0, 0, 0, 0, 0, 0), 'b'),
137 DO(BRLAPI_DOTS(1, 0, 0, 1, 0, 0, 0, 0), 'c'),
138 DO(BRLAPI_DOTS(1, 0, 0, 1, 1, 0, 0, 0), 'd'),
139 DO(BRLAPI_DOTS(1, 0, 0, 0, 1, 0, 0, 0), 'e'),
140 DO(BRLAPI_DOTS(1, 1, 0, 1, 0, 0, 0, 0), 'f'),
[all …]

12345678910>>...59