Lines Matching +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
62 CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
64 1000, OSC-1, -1, -1, 10, 8, 4};
68 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
69 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
70 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
71 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
72 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
73 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
76 {25, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
77 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
78 {25, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
79 {30, 0, 1, -1, -1, -1, -1}, /* OPP 120 */
80 {100, 3, 1, -1, -1, -1, -1}, /* OPP TB */
81 {125, 2, 1, -1, -1, -1, -1} /* OPP NT */
84 {24, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
85 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
86 {24, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
87 {144, 4, 1, -1, -1, -1, -1}, /* OPP 120 */
88 {32, 0, 1, -1, -1, -1, -1}, /* OPP TB */
89 {40, 0, 1, -1, -1, -1, -1} /* OPP NT */
92 {300, 12, 2, -1, -1, -1, -1}, /* OPP 50 */
93 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
94 {300, 12, 1, -1, -1, -1, -1}, /* OPP 100 */
95 {360, 12, 1, -1, -1, -1, -1}, /* OPP 120 */
96 {400, 12, 1, -1, -1, -1, -1}, /* OPP TB */
97 {500, 12, 1, -1, -1, -1, -1} /* OPP NT */
102 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
103 {125, 2, -1, -1, 10, 8, 4}, /* 24 MHz */
104 {40, 0, -1, -1, 10, 8, 4}, /* 25 MHz */
105 {500, 12, -1, -1, 10, 8, 4} /* 26 MHz */
109 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
110 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
111 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
112 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
116 {505, 15, 2, -1, -1, -1, -1}, /*19.2*/
117 {101, 3, 2, -1, -1, -1, -1}, /* 24 MHz */
118 {303, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
119 {303, 12, 2, -1, -1, -1, -1} /* 26 MHz */
123 {125, 5, 1, -1, -1, -1, -1}, /*19.2*/
124 {50, 2, 1, -1, -1, -1, -1}, /* 24 MHz */
125 {16, 0, 1, -1, -1, -1, -1}, /* 25 MHz */
126 {200, 12, 1, -1, -1, -1, -1} /* 26 MHz */
130 {665, 47, 1, -1, -1, -1, -1}, /*19.2*/
131 {133, 11, 1, -1, -1, -1, -1}, /* 24 MHz */
132 {266, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
133 {133, 12, 1, -1, -1, -1, -1} /* 26 MHz */
157 clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, in setup_clocks_for_console()
161 clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, in setup_clocks_for_console()
165 clrsetbits_le32(&cmwkup->wkup_uart0ctrl, in setup_clocks_for_console()
169 clrsetbits_le32(&cmper->uart1clkctrl, in setup_clocks_for_console()
173 clrsetbits_le32(&cmper->uart2clkctrl, in setup_clocks_for_console()
177 clrsetbits_le32(&cmper->uart3clkctrl, in setup_clocks_for_console()
181 clrsetbits_le32(&cmper->uart4clkctrl, in setup_clocks_for_console()
185 clrsetbits_le32(&cmper->uart5clkctrl, in setup_clocks_for_console()
194 &cmper->l3clkstctrl, in enable_basic_clocks()
195 &cmper->l4fwclkstctrl, in enable_basic_clocks()
196 &cmper->l3sclkstctrl, in enable_basic_clocks()
197 &cmper->l4lsclkstctrl, in enable_basic_clocks()
198 &cmwkup->wkclkstctrl, in enable_basic_clocks()
199 &cmper->emiffwclkctrl, in enable_basic_clocks()
200 &cmrtc->clkstctrl, in enable_basic_clocks()
205 &cmper->l3clkctrl, in enable_basic_clocks()
206 &cmper->l4lsclkctrl, in enable_basic_clocks()
207 &cmper->l4fwclkctrl, in enable_basic_clocks()
208 &cmwkup->wkl4wkclkctrl, in enable_basic_clocks()
209 &cmper->l3instrclkctrl, in enable_basic_clocks()
210 &cmper->l4hsclkctrl, in enable_basic_clocks()
211 &cmwkup->wkgpio0clkctrl, in enable_basic_clocks()
212 &cmwkup->wkctrlclkctrl, in enable_basic_clocks()
213 &cmper->timer2clkctrl, in enable_basic_clocks()
214 &cmper->gpmcclkctrl, in enable_basic_clocks()
215 &cmper->elmclkctrl, in enable_basic_clocks()
216 &cmper->mmc0clkctrl, in enable_basic_clocks()
217 &cmper->mmc1clkctrl, in enable_basic_clocks()
218 &cmwkup->wkup_i2c0ctrl, in enable_basic_clocks()
219 &cmper->gpio1clkctrl, in enable_basic_clocks()
220 &cmper->gpio2clkctrl, in enable_basic_clocks()
221 &cmper->gpio3clkctrl, in enable_basic_clocks()
222 &cmper->i2c1clkctrl, in enable_basic_clocks()
223 &cmper->cpgmac0clkctrl, in enable_basic_clocks()
224 &cmper->spi0clkctrl, in enable_basic_clocks()
225 &cmrtc->rtcclkctrl, in enable_basic_clocks()
226 &cmper->usb0clkctrl, in enable_basic_clocks()
227 &cmper->emiffwclkctrl, in enable_basic_clocks()
228 &cmper->emifclkctrl, in enable_basic_clocks()
232 do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); in enable_basic_clocks()
235 writel(0x1, &cmdpll->clktimer2clk); in enable_basic_clocks()
260 cm_clksel_dpll_mpu = readl(&cmwkup->clkseldpllmpu); in set_mpu_spreadspectrum()
265 * Calculate reference clock (clock after pre-divider), in set_mpu_spreadspectrum()
269 ref_clock = V_OSCK / (predivider_n + 1); in set_mpu_spreadspectrum()
298 writel(delta_m_step, &cmwkup->sscdeltamstepdllmpu); in set_mpu_spreadspectrum()
299 writel((exponent << 8) | mantissa, &cmwkup->sscmodfreqdivdpllmpu); in set_mpu_spreadspectrum()
300 cm_clkmode_dpll_mpu = readl(&cmwkup->clkmoddpllmpu); in set_mpu_spreadspectrum()
306 writel(cm_clkmode_dpll_mpu, &cmwkup->clkmoddpllmpu); in set_mpu_spreadspectrum()
307 while (!(readl(&cmwkup->clkmoddpllmpu) & 0x2000)) in set_mpu_spreadspectrum()