1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2c74b2108SSergey Kubushyn /* 3c74b2108SSergey Kubushyn * DP83848 ethernet Physical layer 4c74b2108SSergey Kubushyn * 5c74b2108SSergey Kubushyn * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 6c74b2108SSergey Kubushyn * 7c74b2108SSergey Kubushyn */ 8c74b2108SSergey Kubushyn 9c74b2108SSergey Kubushyn 10c74b2108SSergey Kubushyn /* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */ 11c74b2108SSergey Kubushyn 12c74b2108SSergey Kubushyn #define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */ 13c74b2108SSergey Kubushyn #define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */ 14c74b2108SSergey Kubushyn #define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */ 15c74b2108SSergey Kubushyn #define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */ 16c74b2108SSergey Kubushyn #define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */ 17c74b2108SSergey Kubushyn #define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */ 18c74b2108SSergey Kubushyn #define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */ 19c74b2108SSergey Kubushyn #define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */ 20c74b2108SSergey Kubushyn #define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */ 21c74b2108SSergey Kubushyn #define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */ 22c74b2108SSergey Kubushyn 23c74b2108SSergey Kubushyn /*--Bit definitions: DP83848_CTL_REG */ 24c74b2108SSergey Kubushyn #define DP83848_RESET (1 << 15) /* 1= S/W Reset */ 25c74b2108SSergey Kubushyn #define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */ 26c74b2108SSergey Kubushyn #define DP83848_SPEED_SELECT (1 << 13) 27c74b2108SSergey Kubushyn #define DP83848_AUTONEG (1 << 12) 28c74b2108SSergey Kubushyn #define DP83848_POWER_DOWN (1 << 11) 29c74b2108SSergey Kubushyn #define DP83848_ISOLATE (1 << 10) 30c74b2108SSergey Kubushyn #define DP83848_RESTART_AUTONEG (1 << 9) 31c74b2108SSergey Kubushyn #define DP83848_DUPLEX_MODE (1 << 8) 32c74b2108SSergey Kubushyn #define DP83848_COLLISION_TEST (1 << 7) 33c74b2108SSergey Kubushyn 34c74b2108SSergey Kubushyn /*--Bit definitions: DP83848_STAT_REG */ 35c74b2108SSergey Kubushyn #define DP83848_100BASE_T4 (1 << 15) 36c74b2108SSergey Kubushyn #define DP83848_100BASE_TX_FD (1 << 14) 37c74b2108SSergey Kubushyn #define DP83848_100BASE_TX_HD (1 << 13) 38c74b2108SSergey Kubushyn #define DP83848_10BASE_T_FD (1 << 12) 39c74b2108SSergey Kubushyn #define DP83848_10BASE_T_HD (1 << 11) 40c74b2108SSergey Kubushyn #define DP83848_MF_PREAMB_SUPPR (1 << 6) 41c74b2108SSergey Kubushyn #define DP83848_AUTONEG_COMP (1 << 5) 42c74b2108SSergey Kubushyn #define DP83848_RMT_FAULT (1 << 4) 43c74b2108SSergey Kubushyn #define DP83848_AUTONEG_ABILITY (1 << 3) 44c74b2108SSergey Kubushyn #define DP83848_LINK_STATUS (1 << 2) 45c74b2108SSergey Kubushyn #define DP83848_JABBER_DETECT (1 << 1) 46c74b2108SSergey Kubushyn #define DP83848_EXTEND_CAPAB (1 << 0) 47c74b2108SSergey Kubushyn 48c74b2108SSergey Kubushyn /*--definitions: DP83848_PHYID1 */ 49c74b2108SSergey Kubushyn #define DP83848_PHYID1_OUI 0x2000 50c74b2108SSergey Kubushyn #define DP83848_PHYID2_OUI 0x5c90 51c74b2108SSergey Kubushyn 52c74b2108SSergey Kubushyn /*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */ 53c74b2108SSergey Kubushyn #define DP83848_NP (1 << 15) 54c74b2108SSergey Kubushyn #define DP83848_ACK (1 << 14) 55c74b2108SSergey Kubushyn #define DP83848_RF (1 << 13) 56c74b2108SSergey Kubushyn #define DP83848_PAUSE (1 << 10) 57c74b2108SSergey Kubushyn #define DP83848_T4 (1 << 9) 58c74b2108SSergey Kubushyn #define DP83848_TX_FDX (1 << 8) 59c74b2108SSergey Kubushyn #define DP83848_TX_HDX (1 << 7) 60c74b2108SSergey Kubushyn #define DP83848_10_FDX (1 << 6) 61c74b2108SSergey Kubushyn #define DP83848_10_HDX (1 << 5) 62c74b2108SSergey Kubushyn #define DP83848_AN_IEEE_802_3 0x0001 63c74b2108SSergey Kubushyn 64c74b2108SSergey Kubushyn /*--Bit definitions: DP83848_ANER */ 65c74b2108SSergey Kubushyn #define DP83848_PDF (1 << 4) 66c74b2108SSergey Kubushyn #define DP83848_LP_NP_ABLE (1 << 3) 67c74b2108SSergey Kubushyn #define DP83848_NP_ABLE (1 << 2) 68c74b2108SSergey Kubushyn #define DP83848_PAGE_RX (1 << 1) 69c74b2108SSergey Kubushyn #define DP83848_LP_AN_ABLE (1 << 0) 70c74b2108SSergey Kubushyn 71c74b2108SSergey Kubushyn /*--Bit definitions: DP83848_PHY_STAT */ 72c74b2108SSergey Kubushyn #define DP83848_RX_ERR_LATCH (1 << 13) 73c74b2108SSergey Kubushyn #define DP83848_POLARITY_STAT (1 << 12) 74c74b2108SSergey Kubushyn #define DP83848_FALSE_CAR_SENSE (1 << 11) 75c74b2108SSergey Kubushyn #define DP83848_SIG_DETECT (1 << 10) 76c74b2108SSergey Kubushyn #define DP83848_DESCRAM_LOCK (1 << 9) 77c74b2108SSergey Kubushyn #define DP83848_PAGE_RCV (1 << 8) 78c74b2108SSergey Kubushyn #define DP83848_PHY_RMT_FAULT (1 << 6) 79c74b2108SSergey Kubushyn #define DP83848_JABBER (1 << 5) 80c74b2108SSergey Kubushyn #define DP83848_AUTONEG_COMPLETE (1 << 4) 81c74b2108SSergey Kubushyn #define DP83848_LOOPBACK_STAT (1 << 3) 82c74b2108SSergey Kubushyn #define DP83848_DUPLEX (1 << 2) 83c74b2108SSergey Kubushyn #define DP83848_SPEED (1 << 1) 84c74b2108SSergey Kubushyn #define DP83848_LINK (1 << 0) 85