1 // SPDX-License-Identifier: GPL-2.0+
19  *                               NINT + -------------
20  *                XTAL [MHz]              2^(18 - 1)
21  *   PLL [MHz] = ------------ * ----------------------
25  * The vendor U-Boot port contains macros for various combinations of
33 	/* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
47 	{ 300, 300, 150, { 1, 1, 1, { 24, 15 } }, { 1, 1, 1, { 24, 15 } } },
48 	{ 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } },
49 	{ 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } },
50 	{ 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } },
51 	{ 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } },
52 	{ 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } },
53 	{ 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } },
54 	{ 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } },
55 	{ 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } },
56 	{ 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } },
57 	{ 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } },
58 	{ 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } },
59 	{ 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } },
60 	{ 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
61 	{ 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
62 	{ 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } },
63 	{ 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
64 	{ 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
65 	{ 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } },
66 	{ 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } },
67 	{ 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } },
68 	{ 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } },
69 	{ 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } },
70 	{ 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } },
71 	{ 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } },
72 	{ 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } },
73 	{ 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } },
74 	{ 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } },
92 		wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0);  in ar934x_srif_pll_cfg()
118 	writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */  in ar934x_pll_init()
123 		xtal_40 = 1;  in ar934x_pll_init()
143 		pll_nint = pll_cfg->nint[xtal_40];  in ar934x_pll_init()
144 		pll_refdiv = pll_cfg->refdiv;  in ar934x_pll_init()
148 			(pll_cfg->range << AR934X_PLL_CPU_CONFIG_RANGE_SHIFT) |  in ar934x_pll_init()
149 			(pll_cfg->outdiv << AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT);  in ar934x_pll_init()
152 		pll_nint = pll_cfg->nint[xtal_40];  in ar934x_pll_init()
153 		pll_refdiv = pll_cfg->refdiv;  in ar934x_pll_init()
157 			(pll_cfg->range << AR934X_PLL_DDR_CONFIG_RANGE_SHIFT) |  in ar934x_pll_init()
158 			(pll_cfg->outdiv << AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT);  in ar934x_pll_init()
186 	       (1 << AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) |  in ar934x_pll_init()
192 	/* Configure SRIF PLLs, which is completely undocumented :-) */  in ar934x_pll_init()
205 	writel((1 << AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT) |  in ar934x_pll_init()
240 	return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));  in ar934x_cpupll_to_hz()
255 	return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));  in ar934x_ddrpll_to_hz()
303 	gd->cpu_clk = cpuclk / (cpudiv + 1);  in ar934x_update_clock()
304 	gd->mem_clk = ddrclk / (ddrdiv + 1);  in ar934x_update_clock()
305 	gd->bus_clk = busclk / (busdiv + 1);  in ar934x_update_clock()
311 	return gd->bus_clk;  in get_bus_freq()
317 	return gd->mem_clk;  in get_ddr_freq()
323 	printf("CPU:       %8ld MHz\n", gd->cpu_clk / 1000000);  in do_ar934x_showclk()
324 	printf("Memory:    %8ld MHz\n", gd->mem_clk / 1000000);  in do_ar934x_showclk()
325 	printf("AHB:       %8ld MHz\n", gd->bus_clk / 1000000);  in do_ar934x_showclk()
330 	clocks,	CONFIG_SYS_MAXARGS, 1, do_ar934x_showclk,