1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2aed2fbefSSimon Glass /* 3aed2fbefSSimon Glass * (C) Copyright 2003, 2004 4aed2fbefSSimon Glass * ARM Ltd. 5aed2fbefSSimon Glass * Philippe Robin, <philippe.robin@arm.com> 6aed2fbefSSimon Glass */ 7aed2fbefSSimon Glass 8aed2fbefSSimon Glass /* 9aed2fbefSSimon Glass * ARM PrimeCell UART's (PL010 & PL011) 10aed2fbefSSimon Glass * ------------------------------------ 11aed2fbefSSimon Glass * 12aed2fbefSSimon Glass * Definitions common to both PL010 & PL011 13aed2fbefSSimon Glass * 14aed2fbefSSimon Glass */ 15aed2fbefSSimon Glass 16aed2fbefSSimon Glass #ifndef __ASSEMBLY__ 17aed2fbefSSimon Glass /* 18aed2fbefSSimon Glass * We can use a combined structure for PL010 and PL011, because they overlap 19aed2fbefSSimon Glass * only in common registers. 20aed2fbefSSimon Glass */ 21aed2fbefSSimon Glass struct pl01x_regs { 22aed2fbefSSimon Glass u32 dr; /* 0x00 Data register */ 23aed2fbefSSimon Glass u32 ecr; /* 0x04 Error clear register (Write) */ 24aed2fbefSSimon Glass u32 pl010_lcrh; /* 0x08 Line control register, high byte */ 25aed2fbefSSimon Glass u32 pl010_lcrm; /* 0x0C Line control register, middle byte */ 26aed2fbefSSimon Glass u32 pl010_lcrl; /* 0x10 Line control register, low byte */ 27aed2fbefSSimon Glass u32 pl010_cr; /* 0x14 Control register */ 28aed2fbefSSimon Glass u32 fr; /* 0x18 Flag register (Read only) */ 29aed2fbefSSimon Glass #ifdef CONFIG_PL011_SERIAL_RLCR 30aed2fbefSSimon Glass u32 pl011_rlcr; /* 0x1c Receive line control register */ 31aed2fbefSSimon Glass #else 32aed2fbefSSimon Glass u32 reserved; 33aed2fbefSSimon Glass #endif 34aed2fbefSSimon Glass u32 ilpr; /* 0x20 IrDA low-power counter register */ 35aed2fbefSSimon Glass u32 pl011_ibrd; /* 0x24 Integer baud rate register */ 36aed2fbefSSimon Glass u32 pl011_fbrd; /* 0x28 Fractional baud rate register */ 37aed2fbefSSimon Glass u32 pl011_lcrh; /* 0x2C Line control register */ 38aed2fbefSSimon Glass u32 pl011_cr; /* 0x30 Control register */ 39aed2fbefSSimon Glass }; 406001985fSAlexander Graf 416001985fSAlexander Graf #ifdef CONFIG_DM_SERIAL 426001985fSAlexander Graf 436001985fSAlexander Graf int pl01x_serial_ofdata_to_platdata(struct udevice *dev); 446001985fSAlexander Graf int pl01x_serial_probe(struct udevice *dev); 45c9bf43ddSAlexander Graf 46c9bf43ddSAlexander Graf /* Needed for external pl01x_serial_ops drivers */ 47c9bf43ddSAlexander Graf int pl01x_serial_putc(struct udevice *dev, const char ch); 48c9bf43ddSAlexander Graf int pl01x_serial_pending(struct udevice *dev, bool input); 49c9bf43ddSAlexander Graf int pl01x_serial_getc(struct udevice *dev); 50c9bf43ddSAlexander Graf int pl01x_serial_setbrg(struct udevice *dev, int baudrate); 516001985fSAlexander Graf 526001985fSAlexander Graf struct pl01x_priv { 536001985fSAlexander Graf struct pl01x_regs *regs; 546001985fSAlexander Graf enum pl01x_type type; 556001985fSAlexander Graf }; 566001985fSAlexander Graf 576001985fSAlexander Graf #endif /* CONFIG_DM_SERIAL */ 586001985fSAlexander Graf #endif /* !__ASSEMBLY__ */ 59aed2fbefSSimon Glass 60aed2fbefSSimon Glass #define UART_PL01x_RSR_OE 0x08 61aed2fbefSSimon Glass #define UART_PL01x_RSR_BE 0x04 62aed2fbefSSimon Glass #define UART_PL01x_RSR_PE 0x02 63aed2fbefSSimon Glass #define UART_PL01x_RSR_FE 0x01 64aed2fbefSSimon Glass 65aed2fbefSSimon Glass #define UART_PL01x_FR_TXFE 0x80 66aed2fbefSSimon Glass #define UART_PL01x_FR_RXFF 0x40 67aed2fbefSSimon Glass #define UART_PL01x_FR_TXFF 0x20 68aed2fbefSSimon Glass #define UART_PL01x_FR_RXFE 0x10 69aed2fbefSSimon Glass #define UART_PL01x_FR_BUSY 0x08 70aed2fbefSSimon Glass #define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY) 71aed2fbefSSimon Glass 72aed2fbefSSimon Glass /* 73aed2fbefSSimon Glass * PL010 definitions 74aed2fbefSSimon Glass * 75aed2fbefSSimon Glass */ 76aed2fbefSSimon Glass #define UART_PL010_CR_LPE (1 << 7) 77aed2fbefSSimon Glass #define UART_PL010_CR_RTIE (1 << 6) 78aed2fbefSSimon Glass #define UART_PL010_CR_TIE (1 << 5) 79aed2fbefSSimon Glass #define UART_PL010_CR_RIE (1 << 4) 80aed2fbefSSimon Glass #define UART_PL010_CR_MSIE (1 << 3) 81aed2fbefSSimon Glass #define UART_PL010_CR_IIRLP (1 << 2) 82aed2fbefSSimon Glass #define UART_PL010_CR_SIREN (1 << 1) 83aed2fbefSSimon Glass #define UART_PL010_CR_UARTEN (1 << 0) 84aed2fbefSSimon Glass 85aed2fbefSSimon Glass #define UART_PL010_LCRH_WLEN_8 (3 << 5) 86aed2fbefSSimon Glass #define UART_PL010_LCRH_WLEN_7 (2 << 5) 87aed2fbefSSimon Glass #define UART_PL010_LCRH_WLEN_6 (1 << 5) 88aed2fbefSSimon Glass #define UART_PL010_LCRH_WLEN_5 (0 << 5) 89aed2fbefSSimon Glass #define UART_PL010_LCRH_FEN (1 << 4) 90aed2fbefSSimon Glass #define UART_PL010_LCRH_STP2 (1 << 3) 91aed2fbefSSimon Glass #define UART_PL010_LCRH_EPS (1 << 2) 92aed2fbefSSimon Glass #define UART_PL010_LCRH_PEN (1 << 1) 93aed2fbefSSimon Glass #define UART_PL010_LCRH_BRK (1 << 0) 94aed2fbefSSimon Glass 95aed2fbefSSimon Glass 96aed2fbefSSimon Glass #define UART_PL010_BAUD_460800 1 97aed2fbefSSimon Glass #define UART_PL010_BAUD_230400 3 98aed2fbefSSimon Glass #define UART_PL010_BAUD_115200 7 99aed2fbefSSimon Glass #define UART_PL010_BAUD_57600 15 100aed2fbefSSimon Glass #define UART_PL010_BAUD_38400 23 101aed2fbefSSimon Glass #define UART_PL010_BAUD_19200 47 102aed2fbefSSimon Glass #define UART_PL010_BAUD_14400 63 103aed2fbefSSimon Glass #define UART_PL010_BAUD_9600 95 104aed2fbefSSimon Glass #define UART_PL010_BAUD_4800 191 105aed2fbefSSimon Glass #define UART_PL010_BAUD_2400 383 106aed2fbefSSimon Glass #define UART_PL010_BAUD_1200 767 107aed2fbefSSimon Glass /* 108aed2fbefSSimon Glass * PL011 definitions 109aed2fbefSSimon Glass * 110aed2fbefSSimon Glass */ 111aed2fbefSSimon Glass #define UART_PL011_LCRH_SPS (1 << 7) 112aed2fbefSSimon Glass #define UART_PL011_LCRH_WLEN_8 (3 << 5) 113aed2fbefSSimon Glass #define UART_PL011_LCRH_WLEN_7 (2 << 5) 114aed2fbefSSimon Glass #define UART_PL011_LCRH_WLEN_6 (1 << 5) 115aed2fbefSSimon Glass #define UART_PL011_LCRH_WLEN_5 (0 << 5) 116aed2fbefSSimon Glass #define UART_PL011_LCRH_FEN (1 << 4) 117aed2fbefSSimon Glass #define UART_PL011_LCRH_STP2 (1 << 3) 118aed2fbefSSimon Glass #define UART_PL011_LCRH_EPS (1 << 2) 119aed2fbefSSimon Glass #define UART_PL011_LCRH_PEN (1 << 1) 120aed2fbefSSimon Glass #define UART_PL011_LCRH_BRK (1 << 0) 121aed2fbefSSimon Glass 122aed2fbefSSimon Glass #define UART_PL011_CR_CTSEN (1 << 15) 123aed2fbefSSimon Glass #define UART_PL011_CR_RTSEN (1 << 14) 124aed2fbefSSimon Glass #define UART_PL011_CR_OUT2 (1 << 13) 125aed2fbefSSimon Glass #define UART_PL011_CR_OUT1 (1 << 12) 126aed2fbefSSimon Glass #define UART_PL011_CR_RTS (1 << 11) 127aed2fbefSSimon Glass #define UART_PL011_CR_DTR (1 << 10) 128aed2fbefSSimon Glass #define UART_PL011_CR_RXE (1 << 9) 129aed2fbefSSimon Glass #define UART_PL011_CR_TXE (1 << 8) 130aed2fbefSSimon Glass #define UART_PL011_CR_LPE (1 << 7) 131aed2fbefSSimon Glass #define UART_PL011_CR_IIRLP (1 << 2) 132aed2fbefSSimon Glass #define UART_PL011_CR_SIREN (1 << 1) 133aed2fbefSSimon Glass #define UART_PL011_CR_UARTEN (1 << 0) 134aed2fbefSSimon Glass 135aed2fbefSSimon Glass #define UART_PL011_IMSC_OEIM (1 << 10) 136aed2fbefSSimon Glass #define UART_PL011_IMSC_BEIM (1 << 9) 137aed2fbefSSimon Glass #define UART_PL011_IMSC_PEIM (1 << 8) 138aed2fbefSSimon Glass #define UART_PL011_IMSC_FEIM (1 << 7) 139aed2fbefSSimon Glass #define UART_PL011_IMSC_RTIM (1 << 6) 140aed2fbefSSimon Glass #define UART_PL011_IMSC_TXIM (1 << 5) 141aed2fbefSSimon Glass #define UART_PL011_IMSC_RXIM (1 << 4) 142aed2fbefSSimon Glass #define UART_PL011_IMSC_DSRMIM (1 << 3) 143aed2fbefSSimon Glass #define UART_PL011_IMSC_DCDMIM (1 << 2) 144aed2fbefSSimon Glass #define UART_PL011_IMSC_CTSMIM (1 << 1) 145aed2fbefSSimon Glass #define UART_PL011_IMSC_RIMIM (1 << 0) 146