| /openbmc/u-boot/include/synopsys/ |
| H A D | dwcddr21mctl.h | 47 #define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) argument
48 #define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1) argument
49 #define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2) argument
50 #define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) argument
51 #define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) argument
52 #define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) argument
53 #define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14) argument
54 #define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15) argument
55 #define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17) argument
56 #define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27) argument
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| /openbmc/u-boot/board/samsung/odroid/ |
| H A D | setup.h | 11 #define SDIV(x) ((x) & 0x7) argument
12 #define PDIV(x) (((x) & 0x3f) << 8) argument
13 #define MDIV(x) (((x) & 0x3ff) << 16) argument
14 #define FSEL(x) (((x) & 0x1) << 27) argument
16 #define PLL_ENABLE(x) (((x) & 0x1) << 31) argument
19 #define MUX_APLL_SEL(x) ((x) & 0x1) argument
20 #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) argument
21 #define MUX_HPM_SEL(x) (((x) & 0x1) << 20) argument
22 #define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24) argument
27 #define APLL_SEL(x) ((x) & 0x7) argument
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| /openbmc/u-boot/include/andestech/ |
| H A D | andes_pcu.h | 79 #define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) argument
80 #define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) argument
85 #define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) argument
86 #define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) argument
91 #define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) argument
92 #define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) argument
93 #define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) argument
98 #define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) argument
99 #define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) argument
100 #define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) argument
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| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | opcodes.h | 24 #define ___asm_opcode_swab32(x) ( \ argument
30 #define ___asm_opcode_swab16(x) ( \ argument
34 #define ___asm_opcode_swahb32(x) ( \ argument
38 #define ___asm_opcode_swahw32(x) ( \ argument
42 #define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF) argument
43 #define ___asm_opcode_identity16(x) ((x) & 0xFFFF) argument
88 #define ___opcode_swab32(x) swab32(x) argument
89 #define ___opcode_swab16(x) swab16(x) argument
90 #define ___opcode_swahb32(x) swahb32(x) argument
91 #define ___opcode_swahw32(x) swahw32(x) argument
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| /openbmc/u-boot/include/linux/byteorder/ |
| H A D | little_endian.h | 16 #define __constant_htonl(x) ((__force __be32)___constant_swab32((x))) argument
17 #define __constant_ntohl(x) ___constant_swab32((__force __be32)(x)) argument
18 #define __constant_htons(x) ((__force __be16)___constant_swab16((x))) argument
19 #define __constant_ntohs(x) ___constant_swab16((__force __be16)(x)) argument
20 #define __constant_cpu_to_le64(x) ((__force __le64)(__u64)(x)) argument
21 #define __constant_le64_to_cpu(x) ((__force __u64)(__le64)(x)) argument
22 #define __constant_cpu_to_le32(x) ((__force __le32)(__u32)(x)) argument
23 #define __constant_le32_to_cpu(x) ((__force __u32)(__le32)(x)) argument
24 #define __constant_cpu_to_le16(x) ((__force __le16)(__u16)(x)) argument
25 #define __constant_le16_to_cpu(x) ((__force __u16)(__le16)(x)) argument
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| H A D | big_endian.h | 16 #define __constant_htonl(x) ((__force __be32)(__u32)(x)) argument
17 #define __constant_ntohl(x) ((__force __u32)(__be32)(x)) argument
18 #define __constant_htons(x) ((__force __be16)(__u16)(x)) argument
19 #define __constant_ntohs(x) ((__force __u16)(__be16)(x)) argument
20 #define __constant_cpu_to_le64(x) ((__force __le64)___constant_swab64((x))) argument
21 #define __constant_le64_to_cpu(x) ___constant_swab64((__force __u64)(__le64)(x)) argument
22 #define __constant_cpu_to_le32(x) ((__force __le32)___constant_swab32((x))) argument
23 #define __constant_le32_to_cpu(x) ___constant_swab32((__force __u32)(__le32)(x)) argument
24 #define __constant_cpu_to_le16(x) ((__force __le16)___constant_swab16((x))) argument
25 #define __constant_le16_to_cpu(x) ___constant_swab16((__force __u16)(__le16)(x)) argument
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| H A D | swab.h | 21 #define ___swab16(x) \ argument
25 #define ___swab32(x) \ argument
31 #define ___swab64(x) \ argument
46 # define __arch__swab16(x) ___swab16(x) argument
49 # define __arch__swab32(x) ___swab32(x) argument
52 # define __arch__swab64(x) ___swab64(x) argument
56 # define __arch__swab16p(x) __swab16(*(x)) argument
59 # define __arch__swab32p(x) __swab32(*(x)) argument
62 # define __arch__swab64p(x) __swab64(*(x)) argument
66 # define __arch__swab16s(x) do { *(x) = __swab16p((x)); } while (0) argument
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| /openbmc/u-boot/include/ |
| H A D | compiler.h | 70 #define uswap_16(x) \ argument
73 #define uswap_32(x) \ argument
78 #define _uswap_64(x, sfx) \ argument
88 # define uswap_64(x) _uswap_64(x, ull) argument
90 # define uswap_64(x) _uswap_64(x, ) argument
94 # define cpu_to_le16(x) (x) argument
95 # define cpu_to_le32(x) (x) argument
96 # define cpu_to_le64(x) (x) argument
97 # define le16_to_cpu(x) (x) argument
98 # define le32_to_cpu(x) (x) argument
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| H A D | imx_lpi2c.h | 94 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATUR… argument
97 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_… argument
100 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_… argument
105 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIF… argument
108 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIF… argument
113 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIF… argument
116 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIF… argument
119 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SH… argument
122 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SH… argument
125 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIF… argument
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| /openbmc/u-boot/arch/arm/include/asm/arch-omap3/ |
| H A D | omap3-regs.h | 23 #define CLKACTIVATIONTIME(x) (((x) & 3) << 25) argument
24 #define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23) argument
27 #define WAITMONITORINGTIME(x) (((x) & 3) << 18) argument
28 #define WAITPINSELECT(x) (((x) & 3) << 16) argument
29 #define DEVICESIZE(x) (((x) & 3) << 12) argument
32 #define DEVICETYPE(x) (((x) & 3) << 10) argument
37 #define GPMCFCLKDIVIDER(x) (((x) & 3) << 0) argument
40 #define CSWROFFTIME(x) (((x) & 0x1f) << 16) argument
41 #define CSRDOFFTIME(x) (((x) & 0x1f) << 8) argument
43 #define CSONTIME(x) (((x) & 0xf) << 0) argument
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| /openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/ |
| H A D | ocelot_icpu_cfg.h | 9 #define ICPU_GPR(x) (0x4 * (x)) argument
30 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4)) argument
32 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4) argument
41 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) argument
43 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) argument
44 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
54 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) argument
56 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) argument
57 #define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1)) argument
59 #define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1) argument
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| /openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/ |
| H A D | jr2_icpu_cfg.h | 9 #define ICPU_GPR(x) (0x4 * (x)) argument
29 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 6) & GENMASK(7, 6)) argument
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(7, 6)) >> 4) argument
32 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER(x) (((x) << 4) & GENMASK(5, 4)) argument
34 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4) argument
44 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) argument
46 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) argument
47 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
57 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) argument
59 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) argument
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| /openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/ |
| H A D | servalt_icpu_cfg.h | 9 #define ICPU_GPR(x) (0x4 * (x)) argument
30 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4)) argument
32 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4) argument
42 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) argument
44 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) argument
45 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
55 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) argument
57 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) argument
58 #define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1)) argument
60 #define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1) argument
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| /openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/ |
| H A D | serval_icpu_cfg.h | 9 #define ICPU_GPR(x) (0x4 * (x)) argument
37 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) argument
39 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) argument
40 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
50 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) argument
52 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) argument
53 #define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1)) argument
55 #define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1) argument
60 #define ICPU_DST_INTR_MAP(x) (0x94 + 0x4 * (x)) argument
65 #define ICPU_TIMER_VALUE(x) (0xe4 + 0x4 * (x)) argument
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| /openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/ |
| H A D | luton_icpu_cfg.h | 9 #define ICPU_GPR(x) (0x4 * (x)) argument
35 #define ICPU_PI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
41 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) argument
43 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) argument
44 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) argument
54 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) argument
56 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) argument
57 #define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1)) argument
59 #define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1) argument
85 #define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4)) argument
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | vop_rk3288.h | 122 #define V_AUTO_GATING_EN(x) (((x) & 1) << 23) argument
123 #define V_STANDBY_EN(x) (((x) & 1) << 22) argument
124 #define V_DMA_STOP(x) (((x) & 1) << 21) argument
125 #define V_MMU_EN(x) (((x) & 1) << 20) argument
126 #define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18) argument
127 #define V_MIPI_OUT_EN(x) (((x) & 1) << 15) argument
128 #define V_EDP_OUT_EN(x) (((x) & 1) << 14) argument
129 #define V_HDMI_OUT_EN(x) (((x) & 1) << 13) argument
130 #define V_RGB_OUT_EN(x) (((x) & 1) << 12) argument
131 #define V_EDPI_WMS_FS(x) (((x) & 1) << 10) argument
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| /openbmc/u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | psc_defs.h | 23 #define PSC_REG_PDSTAT(x) (0x200 + (4 * (x))) argument
24 #define PSC_REG_PDCTL(x) (0x300 + (4 * (x))) argument
25 #define PSC_REG_MDCFG(x) (0x600 + (4 * (x))) argument
26 #define PSC_REG_MDSTAT(x) (0x800 + (4 * (x))) argument
27 #define PSC_REG_MDCTL(x) (0xa00 + (4 * (x))) argument
30 static inline u32 _boot_bit_mask(u32 x, u32 y) in _boot_bit_mask()
36 static inline u32 boot_read_bitfield(u32 z, u32 x, u32 y) in boot_read_bitfield()
42 static inline u32 boot_set_bitfield(u32 z, u32 f, u32 x, u32 y) in boot_set_bitfield()
50 #define PSC_REG_PDCTL_SET_NEXT(x, y) boot_set_bitfield((x), (y), 0, 0) argument
51 #define PSC_REG_PDCTL_SET_PDMODE(x, y) boot_set_bitfield((x), (y), 15, 12) argument
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| /openbmc/u-boot/arch/arm/mach-socfpga/include/mach/ |
| H A D | sdram_s10.h | 97 #define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ argument
99 #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ argument
101 #define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \ argument
103 #define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \ argument
105 #define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \ argument
108 #define CTRLCFG0_CFG_MEMTYPE(x) \ argument
110 #define CTRLCFG0_CFG_DIMM_TYPE(x) \ argument
112 #define CTRLCFG0_CFG_AC_POS(x) \ argument
114 #define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \ argument
117 #define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \ argument
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| /openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
| H A D | sromc.h | 15 #define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) argument
16 #define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ argument
18 #define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) argument
19 #define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) argument
21 #define SMC_BC_TACS(x) (x << 28) /* 0clk address set-up */ argument
22 #define SMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */ argument
23 #define SMC_BC_TACC(x) (x << 16) /* 14clk access cycle */ argument
24 #define SMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */ argument
25 #define SMC_BC_TAH(x) (x << 8) /* 4clk address holding time */ argument
26 #define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */ argument
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| /openbmc/u-boot/include/linux/ |
| H A D | bitrev.h | 21 static inline u16 __bitrev16(u16 x) in __bitrev16()
26 static inline u32 __bitrev32(u32 x) in __bitrev32()
33 #define __bitrev8x4(x) (__bitrev32(swab32(x))) argument
35 #define __constant_bitrev32(x) \ argument
46 #define __constant_bitrev16(x) \ argument
56 #define __constant_bitrev8x4(x) \ argument
65 #define __constant_bitrev8(x) \ argument
74 #define bitrev32(x) \ argument
82 #define bitrev16(x) \ argument
90 #define bitrev8x4(x) \ argument
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| /openbmc/u-boot/arch/m68k/include/asm/coldfire/ |
| H A D | lcd.h | 50 #define LCDC_SSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) argument
53 #define LCDC_SR_XMAX(x) (((x)&0x0000003F)<<20) argument
54 #define LCDC_SR_YMAX(x) ((x)&0x000003FF) argument
57 #define LCDC_VPWR_VPW(x) (((x)&0x000003FF) argument
60 #define LCDC_CPR_CC(x) (((x)&0x00000003)<<30) argument
66 #define LCDC_CPR_CXP(x) (((x)&0x000003FF)<<16) argument
67 #define LCDC_CPR_CYP(x) ((x)&0x000003FF) argument
71 #define LCDC_CWHBR_CW(x) (((x)&0x0000001F)<<24) argument
72 #define LCDC_CWHBR_CH(x) (((x)&0x0000001F)<<16) argument
73 #define LCDC_CWHBR_BD(x) ((x)&0x000000FF) argument
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| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | sama5d2_smc.h | 32 #define AT91_SMC_SETUP_NWE(x) (x & 0x3f) argument
33 #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) argument
34 #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) argument
35 #define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) argument
37 #define AT91_SMC_PULSE_NWE(x) (x & 0x7f) argument
38 #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) argument
39 #define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) argument
40 #define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) argument
42 #define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) argument
43 #define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) argument
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| H A D | sama5d3_smc.h | 33 #define AT91_SMC_SETUP_NWE(x) (x & 0x3f) argument
34 #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) argument
35 #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) argument
36 #define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) argument
38 #define AT91_SMC_PULSE_NWE(x) (x & 0x3f) argument
39 #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x3f) << 8) argument
40 #define AT91_SMC_PULSE_NRD(x) ((x & 0x3f) << 16) argument
41 #define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x3f) << 24) argument
43 #define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) argument
44 #define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) argument
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| /openbmc/u-boot/arch/mips/include/asm/mach-generic/ |
| H A D | mangle-port.h | 27 # define ioswabb(a, x) (x) argument
28 # define __mem_ioswabb(a, x) (x) argument
29 # define ioswabw(a, x) le16_to_cpu(x) argument
30 # define __mem_ioswabw(a, x) (x) argument
31 # define ioswabl(a, x) le32_to_cpu(x) argument
32 # define __mem_ioswabl(a, x) (x) argument
33 # define ioswabq(a, x) le64_to_cpu(x) argument
34 # define __mem_ioswabq(a, x) (x) argument
38 # define ioswabb(a, x) (x) argument
39 # define __mem_ioswabb(a, x) (x) argument
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| /openbmc/u-boot/arch/m68k/include/asm/ |
| H A D | m5329.h | 17 #define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28) argument
18 #define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24) argument
19 #define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20) argument
20 #define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12) argument
21 #define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8) argument
22 #define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4) argument
39 #define SCM_PACRA_PACR0(x) (((x)&0x0F)<<28) argument
40 #define SCM_PACRA_PACR1(x) (((x)&0x0F)<<24) argument
41 #define SCM_PACRA_PACR2(x) (((x)&0x0F)<<20) argument
47 #define SCM_PACRB_PACR8(x) (((x)&0x0F)<<28) argument
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