1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 248e4851fSLudovic Desroches /* 348e4851fSLudovic Desroches * Copyright (C) 2017 Microchip Corporation. 448e4851fSLudovic Desroches * 548e4851fSLudovic Desroches * Static Memory Controllers (SMC) - System peripherals registers. 648e4851fSLudovic Desroches * Based on SAMA5D2 datasheet. 748e4851fSLudovic Desroches */ 848e4851fSLudovic Desroches 948e4851fSLudovic Desroches #ifndef SAMA5D2_SMC_H 1048e4851fSLudovic Desroches #define SAMA5D2_SMC_H 1148e4851fSLudovic Desroches 1248e4851fSLudovic Desroches #ifdef __ASSEMBLY__ 1348e4851fSLudovic Desroches #define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x700) 1448e4851fSLudovic Desroches #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x704) 1548e4851fSLudovic Desroches #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x708) 1648e4851fSLudovic Desroches #define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x70c) 1748e4851fSLudovic Desroches #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x710) 1848e4851fSLudovic Desroches #else 1948e4851fSLudovic Desroches struct at91_cs { 2048e4851fSLudovic Desroches u32 setup; /* 0x600 SMC Setup Register */ 2148e4851fSLudovic Desroches u32 pulse; /* 0x604 SMC Pulse Register */ 2248e4851fSLudovic Desroches u32 cycle; /* 0x608 SMC Cycle Register */ 2348e4851fSLudovic Desroches u32 timings; /* 0x60C SMC Cycle Register */ 2448e4851fSLudovic Desroches u32 mode; /* 0x610 SMC Mode Register */ 2548e4851fSLudovic Desroches }; 2648e4851fSLudovic Desroches 2748e4851fSLudovic Desroches struct at91_smc { 2848e4851fSLudovic Desroches struct at91_cs cs[4]; 2948e4851fSLudovic Desroches }; 3048e4851fSLudovic Desroches #endif /* __ASSEMBLY__ */ 3148e4851fSLudovic Desroches 3248e4851fSLudovic Desroches #define AT91_SMC_SETUP_NWE(x) (x & 0x3f) 3348e4851fSLudovic Desroches #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) 3448e4851fSLudovic Desroches #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) 3548e4851fSLudovic Desroches #define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) 3648e4851fSLudovic Desroches 3748e4851fSLudovic Desroches #define AT91_SMC_PULSE_NWE(x) (x & 0x7f) 3848e4851fSLudovic Desroches #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) 3948e4851fSLudovic Desroches #define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) 4048e4851fSLudovic Desroches #define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) 4148e4851fSLudovic Desroches 4248e4851fSLudovic Desroches #define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) 4348e4851fSLudovic Desroches #define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) 4448e4851fSLudovic Desroches 4548e4851fSLudovic Desroches #define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf) 4648e4851fSLudovic Desroches #define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4) 4748e4851fSLudovic Desroches #define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8) 4848e4851fSLudovic Desroches #define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12) 4948e4851fSLudovic Desroches #define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16) 5048e4851fSLudovic Desroches #define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24) 5148e4851fSLudovic Desroches #define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28) 5248e4851fSLudovic Desroches #define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31) 5348e4851fSLudovic Desroches 5448e4851fSLudovic Desroches #define AT91_SMC_MODE_RM_NCS 0x00000000 5548e4851fSLudovic Desroches #define AT91_SMC_MODE_RM_NRD 0x00000001 5648e4851fSLudovic Desroches #define AT91_SMC_MODE_WM_NCS 0x00000000 5748e4851fSLudovic Desroches #define AT91_SMC_MODE_WM_NWE 0x00000002 5848e4851fSLudovic Desroches 5948e4851fSLudovic Desroches #define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 6048e4851fSLudovic Desroches #define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 6148e4851fSLudovic Desroches #define AT91_SMC_MODE_EXNW_READY 0x00000030 6248e4851fSLudovic Desroches 6348e4851fSLudovic Desroches #define AT91_SMC_MODE_BAT 0x00000100 6448e4851fSLudovic Desroches #define AT91_SMC_MODE_DBW_8 0x00000000 6548e4851fSLudovic Desroches #define AT91_SMC_MODE_DBW_16 0x00001000 6648e4851fSLudovic Desroches #define AT91_SMC_MODE_DBW_32 0x00002000 6748e4851fSLudovic Desroches #define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) 6848e4851fSLudovic Desroches #define AT91_SMC_MODE_TDF 0x00100000 6948e4851fSLudovic Desroches #define AT91_SMC_MODE_PMEN 0x01000000 7048e4851fSLudovic Desroches #define AT91_SMC_MODE_PS_4 0x00000000 7148e4851fSLudovic Desroches #define AT91_SMC_MODE_PS_8 0x10000000 7248e4851fSLudovic Desroches #define AT91_SMC_MODE_PS_16 0x20000000 7348e4851fSLudovic Desroches #define AT91_SMC_MODE_PS_32 0x30000000 7448e4851fSLudovic Desroches 7548e4851fSLudovic Desroches #endif 76