Lines Matching defs:x
97 #define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ argument
99 #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ argument
101 #define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \ argument
103 #define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \ argument
105 #define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \ argument
108 #define CTRLCFG0_CFG_MEMTYPE(x) \ argument
110 #define CTRLCFG0_CFG_DIMM_TYPE(x) \ argument
112 #define CTRLCFG0_CFG_AC_POS(x) \ argument
114 #define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \ argument
117 #define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \ argument
119 #define CTRLCFG1_CFG_ADDR_ORDER(x) \ argument
121 #define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ argument
124 #define DRAMTIMING0_CFG_TCL(x) \ argument
127 #define CALTIMING0_CFG_ACT_TO_RDWR(x) \ argument
129 #define CALTIMING0_CFG_ACT_TO_PCH(x) \ argument
131 #define CALTIMING0_CFG_ACT_TO_ACT(x) \ argument
133 #define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \ argument
136 #define CALTIMING1_CFG_RD_TO_RD(x) \ argument
138 #define CALTIMING1_CFG_RD_TO_RD_DC(x) \ argument
140 #define CALTIMING1_CFG_RD_TO_RD_DB(x) \ argument
142 #define CALTIMING1_CFG_RD_TO_WR(x) \ argument
144 #define CALTIMING1_CFG_RD_TO_WR_DC(x) \ argument
147 #define CALTIMING2_CFG_RD_TO_WR_DB(x) \ argument
149 #define CALTIMING2_CFG_RD_TO_WR_PCH(x) \ argument
151 #define CALTIMING2_CFG_RD_AP_TO_VALID(x) \ argument
153 #define CALTIMING2_CFG_WR_TO_WR(x) \ argument
155 #define CALTIMING2_CFG_WR_TO_WR_DC(x) \ argument
158 #define CALTIMING3_CFG_WR_TO_WR_DB(x) \ argument
160 #define CALTIMING3_CFG_WR_TO_RD(x) \ argument
162 #define CALTIMING3_CFG_WR_TO_RD_DC(x) \ argument
164 #define CALTIMING3_CFG_WR_TO_RD_DB(x) \ argument
166 #define CALTIMING3_CFG_WR_TO_PCH(x) \ argument
169 #define CALTIMING4_CFG_WR_AP_TO_VALID(x) \ argument
171 #define CALTIMING4_CFG_PCH_TO_VALID(x) \ argument
173 #define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \ argument
175 #define CALTIMING4_CFG_ARF_TO_VALID(x) \ argument
177 #define CALTIMING4_CFG_PDN_TO_VALID(x) \ argument
180 #define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ argument