clk: Add fixed-factor clock driverThis patch adds fixed-factor clock driver which derives clockrate by dividing (div) and multiplying (mult) fixed factorsto a parent clock.Signed-off-by: Atish
clk: Add fixed-factor clock driverThis patch adds fixed-factor clock driver which derives clockrate by dividing (div) and multiplying (mult) fixed factorsto a parent clock.Signed-off-by: Atish Patra <atish.patra@wdc.com>Signed-off-by: Anup Patel <anup.patel@wdc.com>Reviewed-by: Simon Glass <sjg@chromium.org>
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clk: stm32mp1: correctly handle Clock Spreading GeneratorTo activate the csg option, the driver need to set the bit2of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generatorof PLLn enable.
clk: stm32mp1: correctly handle Clock Spreading GeneratorTo activate the csg option, the driver need to set the bit2of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generatorof PLLn enable.Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
clk: Introduce TI System Control Interface (TI SCI) clock driverSome TI Keystone 2 and K3 family of SoCs contain a system controller(like the Power Management Micro Controller (PMMC) on 66AK2G SoC
clk: Introduce TI System Control Interface (TI SCI) clock driverSome TI Keystone 2 and K3 family of SoCs contain a system controller(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs andthe Device Management and Security Controller on AM65x SoCs) that managethe low-level device control (like clocks, resets etc) for the varioushardware modules present on the SoC. These device control operations areprovided to the host processor OS through a communication protocolcalled the TI System Control Interface (TI SCI) protocol.This patch adds a clock driver that communicates to the systemcontroller over the TI SCI protocol for performing clock management ofvarious devices present on the SoC. Various clock functionality isachieved by the means of different TI SCI device operations provided bythe TI SCI framework.This code is loosely based on the drivers/clk/keystone/sci-clk.c driverof the Linux kernel.Reviewed-by: Tom Rini <trini@konsulko.com>Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>Signed-off-by: Vignesh R <vigneshr@ti.com>Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
stm32mp1: clk: support digital bypassHSE and LSE bypass shall support both analog and digital signals.This patch add a way to select digital bypas case in the device treeand set the associated bi
stm32mp1: clk: support digital bypassHSE and LSE bypass shall support both analog and digital signals.This patch add a way to select digital bypas case in the device treeand set the associated bit DIGBYP in RCC_BDCR and RCC_OCEN registerduring clock tree initialization.Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
clk: stm32mp1: add clock tree initializationadd binding and code for clock tree initialization from device treeSigned-off-by: Patrick Delaunay <patrick.delaunay@st.com>
ARC: clk: introduce HSDK CGU clock driverSynopsys HSDK clock controller generates and supplies clocks to variouscontrollers and peripherals within the SoC.Each clock has assigned identifier and
ARC: clk: introduce HSDK CGU clock driverSynopsys HSDK clock controller generates and supplies clocks to variouscontrollers and peripherals within the SoC.Each clock has assigned identifier and client device tree nodes can usethis identifier to specify the clock which they consume. All availableclocks are defined as preprocessor macros in thedt-bindings/clock/snps,hsdk-cgu.h header and can be used in devicetree sources.Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
dm: clk: add clk driver support for stm32h7 SoCsThis driver implements basic clock setup, only clock gatingis implemented.This driver doesn't implement .of_match as it's bindedby MFD RCC driver
dm: clk: add clk driver support for stm32h7 SoCsThis driver implements basic clock setup, only clock gatingis implemented.This driver doesn't implement .of_match as it's bindedby MFD RCC driver.Files include/dt-bindings/clock/stm32h7-clks.h anddoc/device-tree-bindings/clock/st,stm32h7-rcc.txtwill be available soon in a kernel tag, as all thebindings have been acked by Rob Herring [1].[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.htmlSigned-off-by: Patrice Chotard <patrice.chotard@st.com>Reviewed-by: Simon Glass <sjg@chromium.org>
rockchip: rk3368: add DRAM controller driver with DRAM initialisationThis adds a DRAM controller driver for the RK3368 and places it indrivers/ram/rockchip (where the other DM-enabled DRAM control
rockchip: rk3368: add DRAM controller driver with DRAM initialisationThis adds a DRAM controller driver for the RK3368 and places it indrivers/ram/rockchip (where the other DM-enabled DRAM controllerdrivers for rockchip devices should also be moved eventually).At this stage, only the following feature-set is supported: - DDR3 - 32-bit configuration (i.e. fully populated) - dual-rank (i.e. no auto-detection of ranks) - DDR3-1600K speed-binThis driver expects to run from a TPL stage that will later return tothe RK3368 BROM. It communicates with later stages through theos_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDRinit code).Unlike other DMC drivers for RK32xx and RK33xx parts, the requiredtimings are calculated within the driver based on a target frequencyand a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at thistime).The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)register for controlling the operation of its (single-channel) DRAMcontroller in the GRF block. This provides for selecting DDR3, mobileDDR modes, and control low-power operation.As part of this change, DDRC0_CON0 is also added to the GRF structuredefinition (at offset 0x600).Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>Reviewed-by: Simon Glass <sjg@chromium.org>
Merge git://git.denx.de/u-boot-rockchipThis includes support for rk3188 from Heiko Stübner and and rk3328 fromKever Yang. Also included is SPL support for rk3399 and a fix forrk3288 to get it bo
Merge git://git.denx.de/u-boot-rockchipThis includes support for rk3188 from Heiko Stübner and and rk3328 fromKever Yang. Also included is SPL support for rk3399 and a fix forrk3288 to get it booting again (spl_early_init()).
clk: stm32f7: add clock driver for stm32f7 familyadd basic clock driver support for stm32f7 to enable clocks required bythe peripherals.Signed-off-by: Vikas Manocha <vikas.manocha@st.com>Review
clk: stm32f7: add clock driver for stm32f7 familyadd basic clock driver support for stm32f7 to enable clocks required bythe peripherals.Signed-off-by: Vikas Manocha <vikas.manocha@st.com>Reviewed-by: Simon Glass <sjg@chromium.org>
rockchip: arm64: rk3399: add ddr controller driverRK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting fromcoreboot, support 4GB lpddr3 in this version.Signed-off-by: Kever Yang <kever
rockchip: arm64: rk3399: add ddr controller driverRK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting fromcoreboot, support 4GB lpddr3 in this version.Signed-off-by: Kever Yang <kever.yang@rock-chips.com>Added rockchip: tag:Signed-off-by: Simon Glass <sjg@chromium.org>
drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.PIC32 clock module consists of multiple oscillators, PLLs, mutiplexersand dividers capable of supplying clock to various controll
drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.PIC32 clock module consists of multiple oscillators, PLLs, mutiplexersand dividers capable of supplying clock to various controllerson or off-chip.Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>Reviewed-by: Simon Glass <sjg@chromium.org>Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
rockchip: Bring in RK3288 device tree file includes and bindingsBring in required device tree files from Linux. Since mainline Linux issomewhat behind, use the files from the Chromium tree. We can
rockchip: Bring in RK3288 device tree file includes and bindingsBring in required device tree files from Linux. Since mainline Linux issomewhat behind, use the files from the Chromium tree. We can re-sync oncefurther code is acccepted upstream.Signed-off-by: Simon Glass <sjg@chromium.org>
tegra: fdt: Add clock bindingsThis adds a basic binding for the oscillator and peripheral clocks. Thesecond cell is the clock number, defined as the bit number within the clockenable register if
tegra: fdt: Add clock bindingsThis adds a basic binding for the oscillator and peripheral clocks. Thesecond cell is the clock number, defined as the bit number within the clockenable register if the peripheral clock.This uses the RFC clock bindings from Grant Likely so may change later:https://lkml.org/lkml/2011/12/12/498It is taken from Stephen Warren's patch here:http://patchwork.ozlabs.org/patch/141359/Signed-off-by: Simon Glass <sjg@chromium.org>Signed-off-by: Tom Warren <twarren@nvidia.com>