1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <asm/io.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/arch/ns_access.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/fsl_serdes.h> 14 #include <asm/arch/ls102xa_stream_id.h> 15 #include <hwconfig.h> 16 #include <mmc.h> 17 #include <fsl_esdhc.h> 18 #include <fsl_ifc.h> 19 #include <fsl_sec.h> 20 #include <spl.h> 21 22 #include "../common/sleep.h" 23 #include "../common/qixis.h" 24 #include "ls1021aqds_qixis.h" 25 #ifdef CONFIG_U_QE 26 #include "../../../drivers/qe/qe.h" 27 #endif 28 29 #define PIN_MUX_SEL_CAN 0x03 30 #define PIN_MUX_SEL_IIC2 0xa0 31 #define PIN_MUX_SEL_RGMII 0x00 32 #define PIN_MUX_SEL_SAI 0x0c 33 #define PIN_MUX_SEL_SDHC 0x00 34 35 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) 36 #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) 37 DECLARE_GLOBAL_DATA_PTR; 38 39 enum { 40 MUX_TYPE_CAN, 41 MUX_TYPE_IIC2, 42 MUX_TYPE_RGMII, 43 MUX_TYPE_SAI, 44 MUX_TYPE_SDHC, 45 MUX_TYPE_SD_PCI4, 46 MUX_TYPE_SD_PC_SA_SG_SG, 47 MUX_TYPE_SD_PC_SA_PC_SG, 48 MUX_TYPE_SD_PC_SG_SG, 49 }; 50 51 enum { 52 GE0_CLK125, 53 GE2_CLK125, 54 GE1_CLK125, 55 }; 56 57 #ifdef CONFIG_LS102XA_NS_ACCESS 58 static struct csu_ns_dev ns_dev[] = { 59 { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, 60 { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, 61 { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, 62 { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, 63 { CSU_CSLX_OCRAM, CSU_ALL_RW }, 64 { CSU_CSLX_GIC, CSU_ALL_RW }, 65 { CSU_CSLX_PCIE1, CSU_ALL_RW }, 66 { CSU_CSLX_OCRAM2, CSU_ALL_RW }, 67 { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, 68 { CSU_CSLX_PCIE2, CSU_ALL_RW }, 69 { CSU_CSLX_SATA, CSU_ALL_RW }, 70 { CSU_CSLX_USB3, CSU_ALL_RW }, 71 { CSU_CSLX_SERDES, CSU_ALL_RW }, 72 { CSU_CSLX_QDMA, CSU_ALL_RW }, 73 { CSU_CSLX_LPUART2, CSU_ALL_RW }, 74 { CSU_CSLX_LPUART1, CSU_ALL_RW }, 75 { CSU_CSLX_LPUART4, CSU_ALL_RW }, 76 { CSU_CSLX_LPUART3, CSU_ALL_RW }, 77 { CSU_CSLX_LPUART6, CSU_ALL_RW }, 78 { CSU_CSLX_LPUART5, CSU_ALL_RW }, 79 { CSU_CSLX_DSPI2, CSU_ALL_RW }, 80 { CSU_CSLX_DSPI1, CSU_ALL_RW }, 81 { CSU_CSLX_QSPI, CSU_ALL_RW }, 82 { CSU_CSLX_ESDHC, CSU_ALL_RW }, 83 { CSU_CSLX_2D_ACE, CSU_ALL_RW }, 84 { CSU_CSLX_IFC, CSU_ALL_RW }, 85 { CSU_CSLX_I2C1, CSU_ALL_RW }, 86 { CSU_CSLX_USB2, CSU_ALL_RW }, 87 { CSU_CSLX_I2C3, CSU_ALL_RW }, 88 { CSU_CSLX_I2C2, CSU_ALL_RW }, 89 { CSU_CSLX_DUART2, CSU_ALL_RW }, 90 { CSU_CSLX_DUART1, CSU_ALL_RW }, 91 { CSU_CSLX_WDT2, CSU_ALL_RW }, 92 { CSU_CSLX_WDT1, CSU_ALL_RW }, 93 { CSU_CSLX_EDMA, CSU_ALL_RW }, 94 { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, 95 { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, 96 { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, 97 { CSU_CSLX_DDR, CSU_ALL_RW }, 98 { CSU_CSLX_QUICC, CSU_ALL_RW }, 99 { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, 100 { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, 101 { CSU_CSLX_SFP, CSU_ALL_RW }, 102 { CSU_CSLX_TMU, CSU_ALL_RW }, 103 { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, 104 { CSU_CSLX_RESERVED0, CSU_ALL_RW }, 105 { CSU_CSLX_ETSEC1, CSU_ALL_RW }, 106 { CSU_CSLX_SEC5_5, CSU_ALL_RW }, 107 { CSU_CSLX_ETSEC3, CSU_ALL_RW }, 108 { CSU_CSLX_ETSEC2, CSU_ALL_RW }, 109 { CSU_CSLX_GPIO2, CSU_ALL_RW }, 110 { CSU_CSLX_GPIO1, CSU_ALL_RW }, 111 { CSU_CSLX_GPIO4, CSU_ALL_RW }, 112 { CSU_CSLX_GPIO3, CSU_ALL_RW }, 113 { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, 114 { CSU_CSLX_CSU, CSU_ALL_RW }, 115 { CSU_CSLX_ASRC, CSU_ALL_RW }, 116 { CSU_CSLX_SPDIF, CSU_ALL_RW }, 117 { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, 118 { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, 119 { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, 120 { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, 121 { CSU_CSLX_SAI2, CSU_ALL_RW }, 122 { CSU_CSLX_SAI1, CSU_ALL_RW }, 123 { CSU_CSLX_SAI4, CSU_ALL_RW }, 124 { CSU_CSLX_SAI3, CSU_ALL_RW }, 125 { CSU_CSLX_FTM2, CSU_ALL_RW }, 126 { CSU_CSLX_FTM1, CSU_ALL_RW }, 127 { CSU_CSLX_FTM4, CSU_ALL_RW }, 128 { CSU_CSLX_FTM3, CSU_ALL_RW }, 129 { CSU_CSLX_FTM6, CSU_ALL_RW }, 130 { CSU_CSLX_FTM5, CSU_ALL_RW }, 131 { CSU_CSLX_FTM8, CSU_ALL_RW }, 132 { CSU_CSLX_FTM7, CSU_ALL_RW }, 133 { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, 134 { CSU_CSLX_EPU, CSU_ALL_RW }, 135 { CSU_CSLX_GDI, CSU_ALL_RW }, 136 { CSU_CSLX_DDI, CSU_ALL_RW }, 137 { CSU_CSLX_RESERVED1, CSU_ALL_RW }, 138 { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, 139 { CSU_CSLX_RESERVED2, CSU_ALL_RW }, 140 }; 141 #endif 142 143 int checkboard(void) 144 { 145 #ifndef CONFIG_QSPI_BOOT 146 char buf[64]; 147 #endif 148 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) 149 u8 sw; 150 #endif 151 152 puts("Board: LS1021AQDS\n"); 153 154 #ifdef CONFIG_SD_BOOT 155 puts("SD\n"); 156 #elif CONFIG_QSPI_BOOT 157 puts("QSPI\n"); 158 #else 159 sw = QIXIS_READ(brdcfg[0]); 160 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 161 162 if (sw < 0x8) 163 printf("vBank: %d\n", sw); 164 else if (sw == 0x8) 165 puts("PromJet\n"); 166 else if (sw == 0x9) 167 puts("NAND\n"); 168 else if (sw == 0x15) 169 printf("IFCCard\n"); 170 else 171 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 172 #endif 173 174 #ifndef CONFIG_QSPI_BOOT 175 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", 176 QIXIS_READ(id), QIXIS_READ(arch)); 177 178 printf("FPGA: v%d (%s), build %d\n", 179 (int)QIXIS_READ(scver), qixis_read_tag(buf), 180 (int)qixis_read_minor()); 181 #endif 182 183 return 0; 184 } 185 186 unsigned long get_board_sys_clk(void) 187 { 188 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 189 190 switch (sysclk_conf & 0x0f) { 191 case QIXIS_SYSCLK_64: 192 return 64000000; 193 case QIXIS_SYSCLK_83: 194 return 83333333; 195 case QIXIS_SYSCLK_100: 196 return 100000000; 197 case QIXIS_SYSCLK_125: 198 return 125000000; 199 case QIXIS_SYSCLK_133: 200 return 133333333; 201 case QIXIS_SYSCLK_150: 202 return 150000000; 203 case QIXIS_SYSCLK_160: 204 return 160000000; 205 case QIXIS_SYSCLK_166: 206 return 166666666; 207 } 208 return 66666666; 209 } 210 211 unsigned long get_board_ddr_clk(void) 212 { 213 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 214 215 switch ((ddrclk_conf & 0x30) >> 4) { 216 case QIXIS_DDRCLK_100: 217 return 100000000; 218 case QIXIS_DDRCLK_125: 219 return 125000000; 220 case QIXIS_DDRCLK_133: 221 return 133333333; 222 } 223 return 66666666; 224 } 225 226 unsigned int get_soc_major_rev(void) 227 { 228 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 229 unsigned int svr, major; 230 231 svr = in_be32(&gur->svr); 232 major = SVR_MAJ(svr); 233 234 return major; 235 } 236 237 int select_i2c_ch_pca9547(u8 ch) 238 { 239 int ret; 240 241 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); 242 if (ret) { 243 puts("PCA: failed to select proper channel\n"); 244 return ret; 245 } 246 247 return 0; 248 } 249 250 int dram_init(void) 251 { 252 /* 253 * When resuming from deep sleep, the I2C channel may not be 254 * in the default channel. So, switch to the default channel 255 * before accessing DDR SPD. 256 */ 257 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 258 gd->ram_size = initdram(0); 259 260 return 0; 261 } 262 263 #ifdef CONFIG_FSL_ESDHC 264 struct fsl_esdhc_cfg esdhc_cfg[1] = { 265 {CONFIG_SYS_FSL_ESDHC_ADDR}, 266 }; 267 268 int board_mmc_init(bd_t *bis) 269 { 270 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 271 272 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 273 } 274 #endif 275 276 int board_early_init_f(void) 277 { 278 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 279 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 280 unsigned int major; 281 282 #ifdef CONFIG_TSEC_ENET 283 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); 284 #endif 285 286 #ifdef CONFIG_FSL_IFC 287 init_early_memctl_regs(); 288 #endif 289 290 #ifdef CONFIG_FSL_QSPI 291 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 292 #endif 293 294 #ifdef CONFIG_FSL_DCU_FB 295 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); 296 #endif 297 298 /* Configure Little endian for SAI, ASRC and SPDIF */ 299 out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); 300 301 /* 302 * Enable snoop requests and DVM message requests for 303 * Slave insterface S4 (A7 core cluster) 304 */ 305 out_le32(&cci->slave[4].snoop_ctrl, 306 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 307 308 major = get_soc_major_rev(); 309 if (major == SOC_MAJOR_VER_1_0) { 310 /* 311 * Set CCI-400 Slave interface S1, S2 Shareable Override 312 * Register All transactions are treated as non-shareable 313 */ 314 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 315 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 316 317 /* Workaround for the issue that DDR could not respond to 318 * barrier transaction which is generated by executing DSB/ISB 319 * instruction. Set CCI-400 control override register to 320 * terminate the barrier transaction. After DDR is initialized, 321 * allow barrier transaction to DDR again */ 322 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 323 } 324 325 #if defined(CONFIG_DEEP_SLEEP) 326 if (is_warm_boot()) 327 fsl_dp_disable_console(); 328 #endif 329 330 return 0; 331 } 332 333 #ifdef CONFIG_SPL_BUILD 334 void board_init_f(ulong dummy) 335 { 336 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 337 unsigned int major; 338 339 #ifdef CONFIG_NAND_BOOT 340 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; 341 u32 porsr1, pinctl; 342 343 /* 344 * There is LS1 SoC issue where NOR, FPGA are inaccessible during 345 * NAND boot because IFC signals > IFC_AD7 are not enabled. 346 * This workaround changes RCW source to make all signals enabled. 347 */ 348 porsr1 = in_be32(&gur->porsr1); 349 pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | 350 DCFG_CCSR_PORSR1_RCW_SRC_I2C); 351 out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), 352 pinctl); 353 #endif 354 355 /* Clear the BSS */ 356 memset(__bss_start, 0, __bss_end - __bss_start); 357 358 #ifdef CONFIG_FSL_IFC 359 init_early_memctl_regs(); 360 #endif 361 362 get_clocks(); 363 364 #if defined(CONFIG_DEEP_SLEEP) 365 if (is_warm_boot()) 366 fsl_dp_disable_console(); 367 #endif 368 369 preloader_console_init(); 370 371 #ifdef CONFIG_SPL_I2C_SUPPORT 372 i2c_init_all(); 373 #endif 374 375 major = get_soc_major_rev(); 376 if (major == SOC_MAJOR_VER_1_0) 377 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 378 379 dram_init(); 380 381 /* Allow OCRAM access permission as R/W */ 382 #ifdef CONFIG_LS102XA_NS_ACCESS 383 enable_devices_ns_access(&ns_dev[4], 1); 384 enable_devices_ns_access(&ns_dev[7], 1); 385 #endif 386 387 board_init_r(NULL, 0); 388 } 389 #endif 390 391 void config_etseccm_source(int etsec_gtx_125_mux) 392 { 393 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 394 395 switch (etsec_gtx_125_mux) { 396 case GE0_CLK125: 397 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125); 398 debug("etseccm set to GE0_CLK125\n"); 399 break; 400 401 case GE2_CLK125: 402 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); 403 debug("etseccm set to GE2_CLK125\n"); 404 break; 405 406 case GE1_CLK125: 407 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125); 408 debug("etseccm set to GE1_CLK125\n"); 409 break; 410 411 default: 412 printf("Error! trying to set etseccm to invalid value\n"); 413 break; 414 } 415 } 416 417 int config_board_mux(int ctrl_type) 418 { 419 u8 reg12, reg14; 420 421 reg12 = QIXIS_READ(brdcfg[12]); 422 reg14 = QIXIS_READ(brdcfg[14]); 423 424 switch (ctrl_type) { 425 case MUX_TYPE_CAN: 426 config_etseccm_source(GE2_CLK125); 427 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); 428 break; 429 case MUX_TYPE_IIC2: 430 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); 431 break; 432 case MUX_TYPE_RGMII: 433 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); 434 break; 435 case MUX_TYPE_SAI: 436 config_etseccm_source(GE2_CLK125); 437 reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); 438 break; 439 case MUX_TYPE_SDHC: 440 reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); 441 break; 442 case MUX_TYPE_SD_PCI4: 443 reg12 = 0x38; 444 break; 445 case MUX_TYPE_SD_PC_SA_SG_SG: 446 reg12 = 0x01; 447 break; 448 case MUX_TYPE_SD_PC_SA_PC_SG: 449 reg12 = 0x01; 450 break; 451 case MUX_TYPE_SD_PC_SG_SG: 452 reg12 = 0x21; 453 break; 454 default: 455 printf("Wrong mux interface type\n"); 456 return -1; 457 } 458 459 QIXIS_WRITE(brdcfg[12], reg12); 460 QIXIS_WRITE(brdcfg[14], reg14); 461 462 return 0; 463 } 464 465 int config_serdes_mux(void) 466 { 467 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; 468 u32 cfg; 469 470 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; 471 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; 472 473 switch (cfg) { 474 case 0x0: 475 config_board_mux(MUX_TYPE_SD_PCI4); 476 break; 477 case 0x30: 478 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); 479 break; 480 case 0x60: 481 config_board_mux(MUX_TYPE_SD_PC_SG_SG); 482 break; 483 case 0x70: 484 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); 485 break; 486 default: 487 printf("SRDS1 prtcl:0x%x\n", cfg); 488 break; 489 } 490 491 return 0; 492 } 493 494 int misc_init_r(void) 495 { 496 int conflict_flag; 497 498 /* some signals can not enable simultaneous*/ 499 conflict_flag = 0; 500 if (hwconfig("sdhc")) 501 conflict_flag++; 502 if (hwconfig("iic2")) 503 conflict_flag++; 504 if (conflict_flag > 1) { 505 printf("WARNING: pin conflict !\n"); 506 return 0; 507 } 508 509 conflict_flag = 0; 510 if (hwconfig("rgmii")) 511 conflict_flag++; 512 if (hwconfig("can")) 513 conflict_flag++; 514 if (hwconfig("sai")) 515 conflict_flag++; 516 if (conflict_flag > 1) { 517 printf("WARNING: pin conflict !\n"); 518 return 0; 519 } 520 521 if (hwconfig("can")) 522 config_board_mux(MUX_TYPE_CAN); 523 else if (hwconfig("rgmii")) 524 config_board_mux(MUX_TYPE_RGMII); 525 else if (hwconfig("sai")) 526 config_board_mux(MUX_TYPE_SAI); 527 528 if (hwconfig("iic2")) 529 config_board_mux(MUX_TYPE_IIC2); 530 else if (hwconfig("sdhc")) 531 config_board_mux(MUX_TYPE_SDHC); 532 533 #ifdef CONFIG_FSL_CAAM 534 return sec_init(); 535 #endif 536 return 0; 537 } 538 539 struct liodn_id_table sec_liodn_tbl[] = { 540 SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), 541 SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), 542 SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), 543 SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), 544 SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), 545 SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), 546 SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), 547 SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), 548 SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), 549 SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), 550 SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), 551 SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), 552 SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), 553 SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), 554 SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), 555 SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), 556 }; 557 558 struct smmu_stream_id dev_stream_id[] = { 559 { 0x100, 0x01, "ETSEC MAC1" }, 560 { 0x104, 0x02, "ETSEC MAC2" }, 561 { 0x108, 0x03, "ETSEC MAC3" }, 562 { 0x10c, 0x04, "PEX1" }, 563 { 0x110, 0x05, "PEX2" }, 564 { 0x114, 0x06, "qDMA" }, 565 { 0x118, 0x07, "SATA" }, 566 { 0x11c, 0x08, "USB3" }, 567 { 0x120, 0x09, "QE" }, 568 { 0x124, 0x0a, "eSDHC" }, 569 { 0x128, 0x0b, "eMA" }, 570 { 0x14c, 0x0c, "2D-ACE" }, 571 { 0x150, 0x0d, "USB2" }, 572 { 0x18c, 0x0e, "DEBUG" }, 573 }; 574 575 int board_init(void) 576 { 577 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; 578 unsigned int major; 579 580 major = get_soc_major_rev(); 581 if (major == SOC_MAJOR_VER_1_0) { 582 /* Set CCI-400 control override register to 583 * enable barrier transaction */ 584 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 585 } 586 587 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); 588 589 #ifndef CONFIG_SYS_FSL_NO_SERDES 590 fsl_serdes_init(); 591 config_serdes_mux(); 592 #endif 593 594 ls1021x_config_caam_stream_id(sec_liodn_tbl, 595 ARRAY_SIZE(sec_liodn_tbl)); 596 ls102xa_config_smmu_stream_id(dev_stream_id, 597 ARRAY_SIZE(dev_stream_id)); 598 599 #ifdef CONFIG_LS102XA_NS_ACCESS 600 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); 601 #endif 602 603 #ifdef CONFIG_U_QE 604 u_qe_init(); 605 #endif 606 607 return 0; 608 } 609 610 #if defined(CONFIG_DEEP_SLEEP) 611 void board_sleep_prepare(void) 612 { 613 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; 614 unsigned int major; 615 616 major = get_soc_major_rev(); 617 if (major == SOC_MAJOR_VER_1_0) { 618 /* Set CCI-400 control override register to 619 * enable barrier transaction */ 620 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 621 } 622 623 624 #ifdef CONFIG_LS102XA_NS_ACCESS 625 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); 626 #endif 627 } 628 #endif 629 630 int ft_board_setup(void *blob, bd_t *bd) 631 { 632 ft_cpu_setup(blob, bd); 633 634 #ifdef CONFIG_PCI 635 ft_pci_setup(blob, bd); 636 #endif 637 638 return 0; 639 } 640 641 u8 flash_read8(void *addr) 642 { 643 return __raw_readb(addr + 1); 644 } 645 646 void flash_write16(u16 val, void *addr) 647 { 648 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); 649 650 __raw_writew(shftval, addr); 651 } 652 653 u16 flash_read16(void *addr) 654 { 655 u16 val = __raw_readw(addr); 656 657 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); 658 } 659