History log of /openbmc/qemu/target/sparc/ (Results 1 – 25 of 462)
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4482f32d05-Nov-2024 Peter Maydell <peter.maydell@linaro.org>

target/sparc: Explicitly set 2-NaN propagation rule

Set the NaN propagation rule explicitly in the float_status
words we use.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Mark

target/sparc: Explicitly set 2-NaN propagation rule

Set the NaN propagation rule explicitly in the float_status
words we use.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-13-peter.maydell@linaro.org

show more ...

65c1c03905-Nov-2024 Peter Maydell <peter.maydell@linaro.org>

target/sparc: Move cpu_put_fsr(env, 0) call to reset

Currently we call cpu_put_fsr(0) in sparc_cpu_realizefn(), which
initializes various fields in the CPU struct:
* fsr_cexc_ftt
* fcc[]
* fsr_qn

target/sparc: Move cpu_put_fsr(env, 0) call to reset

Currently we call cpu_put_fsr(0) in sparc_cpu_realizefn(), which
initializes various fields in the CPU struct:
* fsr_cexc_ftt
* fcc[]
* fsr_qne
* fsr
It also sets the rounding mode in env->fp_status.

This is largely pointless, because when we later reset the CPU
this will zero out all the fields up until the "end_reset_fields"
label, which includes all of these (but not fp_status!)

Move the cpu_put_fsr(env, 0) call to reset, because that expresses
the logical requirement: we want to reset FSR to 0 on every reset.
This isn't a behaviour change because the fields are all zero anyway.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-12-peter.maydell@linaro.org

show more ...


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b14d064911-Sep-2024 Philippe Mathieu-Daudé <philmd@linaro.org>

license: Update deprecated SPDX tag LGPL-2.0+ to LGPL-2.0-or-later

The 'LGPL-2.0+' license identifier has been deprecated since license
list version 2.0rc2 [1] and replaced by the 'LGPL-2.0-or-later

license: Update deprecated SPDX tag LGPL-2.0+ to LGPL-2.0-or-later

The 'LGPL-2.0+' license identifier has been deprecated since license
list version 2.0rc2 [1] and replaced by the 'LGPL-2.0-or-later' [2]
tag.

[1] https://spdx.org/licenses/LGPL-2.0+.html
[2] https://spdx.org/licenses/LGPL-2.0-or-later.html

Mechanical patch running:

$ sed -i -e s/LGPL-2.0+/LGPL-2.0-or-later/ \
$(git grep -l 'SPDX-License-Identifier: LGPL-2.0+$')

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>

show more ...


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d2a0c3a715-Aug-2024 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Add gen_trap_if_nofpu_fpexception

Model fp_exception state, in which only fp stores are allowed
until such time as the FQ has been flushed.

Signed-off-by: Richard Henderson <richard.h

target/sparc: Add gen_trap_if_nofpu_fpexception

Model fp_exception state, in which only fp stores are allowed
until such time as the FQ has been flushed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Carl Hauser <chauser@pullman.com>

show more ...

29b9980215-Aug-2024 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Implement STDFQ

Invalid encoding of addr should raise TT_ILL_INSN, so
check before supervisor, which might raise TT_PRIV_INSN.
Clear QNE after execution.

Resolves: https://gitlab.com/

target/sparc: Implement STDFQ

Invalid encoding of addr should raise TT_ILL_INSN, so
check before supervisor, which might raise TT_PRIV_INSN.
Clear QNE after execution.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2340
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Carl Hauser <chauser@pullman.com>

show more ...

5a165e2615-Aug-2024 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Add FSR_QNE to tb_flags

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ay

target/sparc: Add FSR_QNE to tb_flags

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Carl Hauser <chauser@pullman.com>

show more ...

c35c8d4d15-Aug-2024 Carl Hauser <chauser@pullman.com>

target/sparc: Populate sparc32 FQ when raising fp exception

Implement a single instruction floating point queue,
populated while delivering an fp exception.

Signed-off-by: Carl Hauser <chauser@pull

target/sparc: Populate sparc32 FQ when raising fp exception

Implement a single instruction floating point queue,
populated while delivering an fp exception.

Signed-off-by: Carl Hauser <chauser@pullman.com>
[rth: Split from a larger patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Carl Hauser <chauser@pullman.com>

show more ...

e412e99715-Aug-2024 Carl Hauser <chauser@pullman.com>

target/sparc: Add FQ and FSR.QNE

Add support for, and migrate, a single-entry fp
instruction queue for sparc32.

Signed-off-by: Carl Hauser <chauser@pullman.com>
[rth: Split from a larger patch;

target/sparc: Add FQ and FSR.QNE

Add support for, and migrate, a single-entry fp
instruction queue for sparc32.

Signed-off-by: Carl Hauser <chauser@pullman.com>
[rth: Split from a larger patch;
adjust representation with union;
add migration state]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Carl Hauser <chauser@pullman.com>

show more ...


/openbmc/qemu/.gitlab-ci.d/buildtest-template.yml
/openbmc/qemu/.gitlab-ci.d/buildtest.yml
/openbmc/qemu/.gitlab-ci.d/cirrus/build.yml
/openbmc/qemu/.gitlab-ci.d/container-cross.yml
/openbmc/qemu/.gitlab-ci.d/crossbuilds.yml
/openbmc/qemu/.gitlab-ci.d/windows.yml
/openbmc/qemu/MAINTAINERS
/openbmc/qemu/Makefile
/openbmc/qemu/VERSION
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/openbmc/qemu/crypto/akcipher-gcrypt.c.inc
/openbmc/qemu/crypto/akcipher-nettle.c.inc
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/openbmc/qemu/crypto/akcipherpriv.h
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12d3629416-Aug-2024 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Restrict STQF to sparcv9

Prior to sparcv9, the same encoding was STDFQ.

Cc: qemu-stable@nongnu.org
Fixes: 06c060d9e5b ("target/sparc: Move simple fp load/store to decodetree")
Signed-

target/sparc: Restrict STQF to sparcv9

Prior to sparcv9, the same encoding was STDFQ.

Cc: qemu-stable@nongnu.org
Fixes: 06c060d9e5b ("target/sparc: Move simple fp load/store to decodetree")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240816072311.353234-2-richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

show more ...


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/openbmc/qemu/tests/tcg/ppc64/Makefile.target
/openbmc/qemu/tests/tcg/riscv64/Makefile.softmmu-target
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/openbmc/qemu/tests/tcg/x86_64/Makefile.softmmu-target
/openbmc/qemu/tests/unit/crypto-tls-psk-helpers.c
/openbmc/qemu/tests/unit/crypto-tls-x509-helpers.c
/openbmc/qemu/tests/unit/crypto-tls-x509-helpers.h
/openbmc/qemu/tests/unit/meson.build
/openbmc/qemu/tests/unit/pkix_asn1_tab.c.inc
/openbmc/qemu/tests/unit/ptimer-test.c
/openbmc/qemu/tests/unit/test-crypto-tlssession.c
/openbmc/qemu/tests/vm/generated/freebsd.json
/openbmc/qemu/tests/vm/openbsd
/openbmc/qemu/tools/i386/qemu-vmsr-helper.c
/openbmc/qemu/tools/i386/rapl-msr-index.h
/openbmc/qemu/ui/console-vc.c
/openbmc/qemu/ui/console.c
/openbmc/qemu/ui/gtk.c
/openbmc/qemu/util/async.c
/openbmc/qemu/util/cpuinfo-aarch64.c
/openbmc/qemu/util/cpuinfo-ppc.c
/openbmc/qemu/util/fifo8.c
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/openbmc/qemu/util/oslib-posix.c
2a48b59021-Jul-2024 Yao Xingtao <yaoxt.fnst@fujitsu.com>

sparc/ldst_helper: make range overlap check more readable

use ranges_overlap() instead of open-coding the overlap check to improve
the readability of the code.

Signed-off-by: Yao Xingtao <yaoxt.fns

sparc/ldst_helper: make range overlap check more readable

use ranges_overlap() instead of open-coding the overlap check to improve
the readability of the code.

Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240722040742.11513-9-yaoxt.fnst@fujitsu.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

show more ...


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/openbmc/qemu/MAINTAINERS
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/openbmc/qemu/tests/tcg/aarch64/sme-fmopa-2.c
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/openbmc/qemu/ui/cocoa.m
/openbmc/qemu/ui/console.c
/openbmc/qemu/ui/cursor.c
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/openbmc/qemu/ui/gtk.c
/openbmc/qemu/ui/sdl2.c
/openbmc/qemu/ui/spice-display.c
/openbmc/qemu/ui/trace-events
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/openbmc/qemu/ui/vnc.c
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/openbmc/qemu/util/oslib-posix.c
4f7b1ecb04-Jul-2024 Peter Maydell <peter.maydell@linaro.org>

target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation

Currently the TCGCPUOps::cpu_exec_halt method is optional, and if it
is not set then the default is to call the CPUClass::has

target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation

Currently the TCGCPUOps::cpu_exec_halt method is optional, and if it
is not set then the default is to call the CPUClass::has_work
method (which has an identical function signature).

We would like to make the cpu_exec_halt method mandatory so we can
remove the runtime check and fallback handling. In preparation for
that, make all the targets which don't need special handling in their
cpu_exec_halt set it to their cpu_has_work implementation instead of
leaving it unset. (This is every target except for arm and i386.)

In the riscv case this requires us to make the function not
be local to the source file it's defined in.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

show more ...


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6b49653706-Jun-2024 Clément Chigot <chigot@adacore.com>

target/sparc: use signed denominator in sdiv helper

The result has to be done with the signed denominator (b32) instead of
the unsigned value passed in argument (b).

Cc: qemu-stable@nongnu.org
Fixe

target/sparc: use signed denominator in sdiv helper

The result has to be done with the signed denominator (b32) instead of
the unsigned value passed in argument (b).

Cc: qemu-stable@nongnu.org
Fixes: 1326010322d6 ("target/sparc: Remove CC_OP_DIV")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2319
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240606144331.698361-1-chigot@adacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...


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/openbmc/qemu/migration/multifd-zlib.c
/openbmc/qemu/migration/multifd-zstd.c
/openbmc/qemu/migration/multifd.c
/openbmc/qemu/migration/multifd.h
/openbmc/qemu/python/scripts/mkvenv.py
/openbmc/qemu/python/scripts/vendor.py
/openbmc/qemu/qapi/migration.json
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/openbmc/qemu/qapi/qmp-dispatch.c
/openbmc/qemu/qapi/qom.json
/openbmc/qemu/qemu-io-cmds.c
/openbmc/qemu/scripts/ci/setup/ubuntu/build-environment.yml
/openbmc/qemu/scripts/ci/setup/ubuntu/ubuntu-2204-aarch64.yaml
/openbmc/qemu/scripts/ci/setup/ubuntu/ubuntu-2204-armhf-cross.yml
/openbmc/qemu/scripts/ci/setup/ubuntu/ubuntu-2204-s390x.yaml
/openbmc/qemu/scripts/kvm/vmxcap
/openbmc/qemu/scripts/meson-buildoptions.sh
/openbmc/qemu/scripts/tracetool/__init__.py
/openbmc/qemu/scripts/update-linux-headers.sh
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/openbmc/qemu/target/hexagon/idef-parser/idef-parser.h
/openbmc/qemu/target/hexagon/idef-parser/idef-parser.y
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/openbmc/qemu/target/hexagon/macros.h
/openbmc/qemu/target/hexagon/op_helper.c
/openbmc/qemu/target/i386/cpu.c
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/openbmc/qemu/target/i386/hvf/hvf.c
/openbmc/qemu/target/i386/hvf/vmx.h
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helper.c
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b12b722705-Nov-2023 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Enable VIS4 feature bit

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

eeb3f59205-Nov-2023 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Implement monitor ASIs

Ignore the "monitor" portion and treat them the same
as their base ASIs.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderso

target/sparc: Implement monitor ASIs

Ignore the "monitor" portion and treat them the same
as their base ASIs.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

6fbc032c05-Nov-2023 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Implement MWAIT

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

56f2ef9c04-Nov-2023 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Implement SUBXC, SUBXCcc

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

db11dfea04-Nov-2023 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Implement FPMIN, FPMAX

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

b3c934dd04-Nov-2023 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Implement VIS4 comparisons

VIS4 completes the set, adding missing signed 8-bit ops
and missing unsigned 16 and 32-bit ops.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Sign

target/sparc: Implement VIS4 comparisons

VIS4 completes the set, adding missing signed 8-bit ops
and missing unsigned 16 and 32-bit ops.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

b99c1bbd04-Nov-2023 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

b2b4849304-Nov-2023 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Implement FALIGNDATAi

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

90b1433d04-Nov-2023 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Add feature bit for VIS4

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

68a414e904-Nov-2023 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Implement IMA extension

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

deadbb1404-Nov-2023 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Enable VIS3 feature bit

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

029b028304-Nov-2023 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Implement XMULX

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

680af1b404-Nov-2023 Richard Henderson <richard.henderson@linaro.org>

target/sparc: Implement UMULXHI

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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