1 /* 2 * QEMU PowerPC PowerNV (POWER8) PHB3 model 3 * 4 * Copyright (c) 2014-2020, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PCI_HOST_PNV_PHB3_H 11 #define PCI_HOST_PNV_PHB3_H 12 13 #include "hw/ppc/xics.h" 14 #include "qom/object.h" 15 #include "hw/pci-host/pnv_phb.h" 16 17 typedef struct PnvPHB3 PnvPHB3; 18 19 /* 20 * PHB3 XICS Source for MSIs 21 */ 22 #define TYPE_PHB3_MSI "phb3-msi" 23 typedef struct Phb3MsiState Phb3MsiState; 24 DECLARE_INSTANCE_CHECKER(Phb3MsiState, PHB3_MSI, 25 TYPE_PHB3_MSI) 26 27 #define PHB3_MAX_MSI 2048 28 29 struct Phb3MsiState { 30 ICSState ics; 31 qemu_irq *qirqs; 32 33 PnvPHB3 *phb; 34 uint64_t rba[PHB3_MAX_MSI / 64]; 35 uint32_t rba_sum; 36 }; 37 38 void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base, 39 uint32_t count); 40 void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data, 41 int32_t dev_pe); 42 void pnv_phb3_msi_ffi(Phb3MsiState *msis, uint64_t val); 43 void pnv_phb3_msi_pic_print_info(Phb3MsiState *msis, GString *buf); 44 45 46 /* 47 * We have one such address space wrapper per possible device under 48 * the PHB since they need to be assigned statically at qemu device 49 * creation time. The relationship to a PE is done later dynamically. 50 * This means we can potentially create a lot of these guys. Q35 51 * stores them as some kind of radix tree but we never really need to 52 * do fast lookups so instead we simply keep a QLIST of them for now, 53 * we can add the radix if needed later on. 54 * 55 * We do cache the PE number to speed things up a bit though. 56 */ 57 typedef struct PnvPhb3DMASpace { 58 PCIBus *bus; 59 uint8_t devfn; 60 int pe_num; /* Cached PE number */ 61 #define PHB_INVALID_PE (-1) 62 PnvPHB3 *phb; 63 AddressSpace dma_as; 64 IOMMUMemoryRegion dma_mr; 65 MemoryRegion msi32_mr; 66 MemoryRegion msi64_mr; 67 QLIST_ENTRY(PnvPhb3DMASpace) list; 68 } PnvPhb3DMASpace; 69 70 /* 71 * PHB3 Power Bus Common Queue 72 */ 73 #define TYPE_PNV_PBCQ "pnv-pbcq" 74 OBJECT_DECLARE_SIMPLE_TYPE(PnvPBCQState, PNV_PBCQ) 75 76 struct PnvPBCQState { 77 DeviceState parent; 78 79 uint32_t nest_xbase; 80 uint32_t spci_xbase; 81 uint32_t pci_xbase; 82 #define PBCQ_NEST_REGS_COUNT 0x46 83 #define PBCQ_PCI_REGS_COUNT 0x15 84 #define PBCQ_SPCI_REGS_COUNT 0x5 85 86 uint64_t nest_regs[PBCQ_NEST_REGS_COUNT]; 87 uint64_t spci_regs[PBCQ_SPCI_REGS_COUNT]; 88 uint64_t pci_regs[PBCQ_PCI_REGS_COUNT]; 89 MemoryRegion mmbar0; 90 MemoryRegion mmbar1; 91 MemoryRegion phbbar; 92 uint64_t mmio0_base; 93 uint64_t mmio0_size; 94 uint64_t mmio1_base; 95 uint64_t mmio1_size; 96 PnvPHB3 *phb; 97 98 MemoryRegion xscom_nest_regs; 99 MemoryRegion xscom_pci_regs; 100 MemoryRegion xscom_spci_regs; 101 }; 102 103 /* 104 * PHB3 PCIe Root Bus 105 */ 106 #define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root" 107 struct PnvPHB3RootBus { 108 PCIBus parent; 109 110 uint32_t chip_id; 111 uint32_t phb_id; 112 }; 113 OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3RootBus, PNV_PHB3_ROOT_BUS) 114 115 /* 116 * PHB3 PCIe Host Bridge for PowerNV machines (POWER8) 117 */ 118 #define TYPE_PNV_PHB3 "pnv-phb3" 119 OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3, PNV_PHB3) 120 121 #define PNV_PHB3_NUM_M64 16 122 #define PNV_PHB3_NUM_REGS (0x1000 >> 3) 123 #define PNV_PHB3_NUM_LSI 8 124 #define PNV_PHB3_NUM_PE 256 125 126 #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) 127 128 struct PnvPHB3 { 129 DeviceState parent; 130 131 PnvPHB *phb_base; 132 133 uint32_t chip_id; 134 uint32_t phb_id; 135 char bus_path[8]; 136 137 uint64_t regs[PNV_PHB3_NUM_REGS]; 138 MemoryRegion mr_regs; 139 140 MemoryRegion mr_m32; 141 MemoryRegion mr_m64[PNV_PHB3_NUM_M64]; 142 MemoryRegion pci_mmio; 143 MemoryRegion pci_io; 144 145 uint64_t ioda_LIST[8]; 146 uint64_t ioda_LXIVT[8]; 147 uint64_t ioda_TVT[512]; 148 uint64_t ioda_M64BT[16]; 149 uint64_t ioda_MDT[256]; 150 uint64_t ioda_PEEV[4]; 151 152 uint32_t total_irq; 153 ICSState lsis; 154 qemu_irq *qirqs; 155 Phb3MsiState msis; 156 157 PnvPBCQState pbcq; 158 159 QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces; 160 161 PnvChip *chip; 162 }; 163 164 uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size); 165 void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size); 166 void pnv_phb3_update_regions(PnvPHB3 *phb); 167 void pnv_phb3_remap_irqs(PnvPHB3 *phb); 168 void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb); 169 170 #endif /* PCI_HOST_PNV_PHB3_H */ 171