#
ad75a51e |
| 13-Sep-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Rename cpu_env to tcg_env
Allow the name 'cpu_env' to be used for something else.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@li
tcg: Rename cpu_env to tcg_env
Allow the name 'cpu_env' to be used for something else.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v8.0.0 |
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#
8cab4157 |
| 01-Apr-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/mips: Tidy helpers for translation
Move most includes from *translate*.c to translate.h, ensuring that we get the ordering correct. Ensure cpu.h is first. Use disas/disas.h instead of exec/l
target/mips: Tidy helpers for translation
Move most includes from *translate*.c to translate.h, ensuring that we get the ordering correct. Ensure cpu.h is first. Use disas/disas.h instead of exec/log.h. Drop otherwise unused includes.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
ac66a187 |
| 24-Feb-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/mips: Drop tcg_temp_free from msa_translate.c
Translators are no longer required to free tcg temporaries.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Hende
target/mips: Drop tcg_temp_free from msa_translate.c
Translators are no longer required to free tcg temporaries.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.2.0 |
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#
1d29f899 |
| 03-May-2022 |
Ni Hui <shuizhuyuanluo@126.com> |
target/mips: Fix FTRUNC_S and FTRUNC_U trans helper
Fix the FTRUNC_S and FTRUNC_U trans helper problem.
Fixes: 5c5b64000c ("target/mips: Convert MSA 2RF instruction format to decodetree") Signed-of
target/mips: Fix FTRUNC_S and FTRUNC_U trans helper
Fix the FTRUNC_S and FTRUNC_U trans helper problem.
Fixes: 5c5b64000c ("target/mips: Convert MSA 2RF instruction format to decodetree") Signed-off-by: nihui <shuizhuyuanluo@126.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220503144241.289239-1-shuizhuyuanluo@126.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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#
ead0bf0d |
| 03-May-2022 |
Ni Hui <shuizhuyuanluo@126.com> |
target/mips: Do not treat msa INSERT as NOP when wd is zero
Only for msa COPY_U/COPY_S with wd zero, we treat it as NOP.
Move this special rule into COPY_U and COPY_S trans function.
Fixes: 97fe67
target/mips: Do not treat msa INSERT as NOP when wd is zero
Only for msa COPY_U/COPY_S with wd zero, we treat it as NOP.
Move this special rule into COPY_U and COPY_S trans function.
Fixes: 97fe675519 ("target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree") Signed-off-by: Ni Hui <shuizhuyuanluo@126.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220503130708.272850-4-shuizhuyuanluo@126.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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#
4b532b4f |
| 03-May-2022 |
Ni Hui <shuizhuyuanluo@126.com> |
target/mips: Fix msa checking condition in trans_msa_elm_fn()
Fix issue that condition of check_msa_enabled(ctx) is reversed that causes segfault when msa elm_fn op encountered.
Fixes: 2f2745c81a (
target/mips: Fix msa checking condition in trans_msa_elm_fn()
Fix issue that condition of check_msa_enabled(ctx) is reversed that causes segfault when msa elm_fn op encountered.
Fixes: 2f2745c81a ("target/mips: Convert MSA COPY_U opcode to decodetree") Fixes: 97fe675519 ("target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree") Signed-off-by: Ni Hui <shuizhuyuanluo@126.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220503130708.272850-3-shuizhuyuanluo@126.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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#
7fc235c6 |
| 03-May-2022 |
Ni Hui <shuizhuyuanluo@126.com> |
target/mips: Fix df_extract_val() and df_extract_df() dfe lookup
Actually look into dfe structure data so that df_extract_val() and df_extract_df() can return immediate and datafield other than BYTE
target/mips: Fix df_extract_val() and df_extract_df() dfe lookup
Actually look into dfe structure data so that df_extract_val() and df_extract_df() can return immediate and datafield other than BYTE.
Fixes: 4701d23aef ("target/mips: Convert MSA BIT instruction format to decodetree") Signed-off-by: Ni Hui <shuizhuyuanluo@126.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220503130708.272850-2-shuizhuyuanluo@126.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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#
954d1658 |
| 03-May-2022 |
Ni Hui <shuizhuyuanluo@126.com> |
target/mips: Fix SAT_S trans helper
Fix the SAT_S and SAT_U trans helper confusion.
Fixes: 4701d23aef ("target/mips: Convert MSA BIT instruction format to decodetree") Signed-off-by: Ni Hui <shuizh
target/mips: Fix SAT_S trans helper
Fix the SAT_S and SAT_U trans helper confusion.
Fixes: 4701d23aef ("target/mips: Convert MSA BIT instruction format to decodetree") Signed-off-by: Ni Hui <shuizhuyuanluo@126.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220503130708.272850-1-shuizhuyuanluo@126.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Revision tags: v7.0.0, v6.2.0 |
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#
75d12c8c |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Remove generic MSA opcode
All opcodes have been converted to decodetree. The generic MSA handler is now pointless, remove it.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewe
target/mips: Remove generic MSA opcode
All opcodes have been converted to decodetree. The generic MSA handler is now pointless, remove it.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-31-f4bug@amsat.org>
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#
643ec902 |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert CTCMSA opcode to decodetree
Convert the CTCMSA (Copy To Control MSA register) opcode to decodetree. Since it overlaps with the SLDI opcode, use a decodetree overlap group.
Revi
target/mips: Convert CTCMSA opcode to decodetree
Convert the CTCMSA (Copy To Control MSA register) opcode to decodetree. Since it overlaps with the SLDI opcode, use a decodetree overlap group.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-30-f4bug@amsat.org>
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#
6f742376 |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert CFCMSA opcode to decodetree
Convert the CFCMSA (Copy From Control MSA register) opcode to decodetree. Since it overlaps with the SPLATI opcode, use a decodetree overlap group.
target/mips: Convert CFCMSA opcode to decodetree
Convert the CFCMSA (Copy From Control MSA register) opcode to decodetree. Since it overlaps with the SPLATI opcode, use a decodetree overlap group.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-29-f4bug@amsat.org>
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#
62ba0e85 |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert MSA MOVE.V opcode to decodetree
Convert the MOVE.V opcode (Vector Move) to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richar
target/mips: Convert MSA MOVE.V opcode to decodetree
Convert the MOVE.V opcode (Vector Move) to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-28-f4bug@amsat.org>
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#
97fe6755 |
| 25-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
Convert the COPY_S (Element Copy to GPR Signed) opcode and INSERT (GPR Insert Element) opcode to decodetree.
Reviewed-by: Jiaxun Yan
target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
Convert the COPY_S (Element Copy to GPR Signed) opcode and INSERT (GPR Insert Element) opcode to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-27-f4bug@amsat.org>
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#
2f2745c8 |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert MSA COPY_U opcode to decodetree
Convert the COPY_U opcode (Element Copy to GPR Unsigned) to decodetree.
Since the 'n' field is a constant value, use tcg_constant_i32() instead
target/mips: Convert MSA COPY_U opcode to decodetree
Convert the COPY_U opcode (Element Copy to GPR Unsigned) to decodetree.
Since the 'n' field is a constant value, use tcg_constant_i32() instead of a TCG temporary.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-26-f4bug@amsat.org>
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#
0a510c93 |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert MSA ELM instruction format to decodetree
Convert instructions with an immediate element index and data format df/n to decodetree.
Since the 'data format' and 'n' fields are con
target/mips: Convert MSA ELM instruction format to decodetree
Convert instructions with an immediate element index and data format df/n to decodetree.
Since the 'data format' and 'n' fields are constant values, use tcg_constant_i32() instead of a TCG temporaries.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-25-f4bug@amsat.org>
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#
0a086d2e |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
Convert 3-register operations to decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxu
target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
Convert 3-register operations to decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-24-f4bug@amsat.org>
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#
c79db8c2 |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit Insert Right) opcodes to decodetree.
Reviewed-by: Jiaxun Yang <j
target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit Insert Right) opcodes to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-23-f4bug@amsat.org>
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#
f18708a5 |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
Convert 3-register operations to decodetree.
Per the Encoding of Operation Field for 3R Instruction Format' (Table 3.25), the
target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
Convert 3-register operations to decodetree.
Per the Encoding of Operation Field for 3R Instruction Format' (Table 3.25), these instructions are not defined for the BYTE format. Therefore the TRANS_DF_iii_b() macro returns 'false' in that case, because no such instruction is decoded.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-22-f4bug@amsat.org>
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#
67bedef5 |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
Convert 3-register operations to decodetree.
Since the 'data format' field is a constant value, use tcg_constant_i32() instea
target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
Convert 3-register operations to decodetree.
Since the 'data format' field is a constant value, use tcg_constant_i32() instead of a TCG temporary.
Note, the format definition could be named @3rf_b (for 3R with a df field BYTE-based) but since the instruction class is named '3R', we simply call the format @3r to ease reviewing the msa.decode file. However we directly call the trans_msa_3rf() function, which handles the BYTE-based df field.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-21-f4bug@amsat.org>
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#
2d5246f3 |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
Convert 3-register floating-point or fixed-point operations to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
Convert 3-register floating-point or fixed-point operations to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-20-f4bug@amsat.org>
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#
ff29e5d3 |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
Convert 3-register floating-point or fixed-point operations to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
Convert 3-register floating-point or fixed-point operations to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211028210843.2120802-19-f4bug@amsat.org>
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#
7acb5c78 |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert MSA VEC instruction format to decodetree
Convert 3-register instructions with implicit data formats to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-b
target/mips: Convert MSA VEC instruction format to decodetree
Convert 3-register instructions with implicit data formats to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-18-f4bug@amsat.org>
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#
adcff99a |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert MSA 2R instruction format to decodetree
Convert 2-register operations to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.
target/mips: Convert MSA 2R instruction format to decodetree
Convert 2-register operations to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-17-f4bug@amsat.org>
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#
675bf34a |
| 19-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert MSA FILL opcode to decodetree
Convert the FILL opcode (Vector Fill from GPR) to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <r
target/mips: Convert MSA FILL opcode to decodetree
Convert the FILL opcode (Vector Fill from GPR) to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-16-f4bug@amsat.org>
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#
5c5b6400 |
| 28-Oct-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
target/mips: Convert MSA 2RF instruction format to decodetree
Convert 2-register floating-point operations to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Hen
target/mips: Convert MSA 2RF instruction format to decodetree
Convert 2-register floating-point operations to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-15-f4bug@amsat.org>
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