1 /* 2 * MIPS SIMD Architecture (MSA) translation routines 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * Copyright (c) 2006 Marius Groeger (FPU operations) 6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) 7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) 8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) 9 * Copyright (c) 2020 Philippe Mathieu-Daudé 10 * 11 * SPDX-License-Identifier: LGPL-2.1-or-later 12 */ 13 #include "qemu/osdep.h" 14 #include "tcg/tcg-op.h" 15 #include "exec/helper-gen.h" 16 #include "translate.h" 17 #include "fpu_helper.h" 18 #include "internal.h" 19 20 static int elm_n(DisasContext *ctx, int x); 21 static int elm_df(DisasContext *ctx, int x); 22 static int bit_m(DisasContext *ctx, int x); 23 static int bit_df(DisasContext *ctx, int x); 24 25 static inline int plus_1(DisasContext *s, int x) 26 { 27 return x + 1; 28 } 29 30 static inline int plus_2(DisasContext *s, int x) 31 { 32 return x + 2; 33 } 34 35 /* Include the auto-generated decoder. */ 36 #include "decode-msa.c.inc" 37 38 #define OPC_MSA (0x1E << 26) 39 40 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 41 enum { 42 OPC_MSA_ELM = 0x19 | OPC_MSA, 43 }; 44 45 enum { 46 /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */ 47 OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, 48 }; 49 50 static const char msaregnames[][6] = { 51 "w0.d0", "w0.d1", "w1.d0", "w1.d1", 52 "w2.d0", "w2.d1", "w3.d0", "w3.d1", 53 "w4.d0", "w4.d1", "w5.d0", "w5.d1", 54 "w6.d0", "w6.d1", "w7.d0", "w7.d1", 55 "w8.d0", "w8.d1", "w9.d0", "w9.d1", 56 "w10.d0", "w10.d1", "w11.d0", "w11.d1", 57 "w12.d0", "w12.d1", "w13.d0", "w13.d1", 58 "w14.d0", "w14.d1", "w15.d0", "w15.d1", 59 "w16.d0", "w16.d1", "w17.d0", "w17.d1", 60 "w18.d0", "w18.d1", "w19.d0", "w19.d1", 61 "w20.d0", "w20.d1", "w21.d0", "w21.d1", 62 "w22.d0", "w22.d1", "w23.d0", "w23.d1", 63 "w24.d0", "w24.d1", "w25.d0", "w25.d1", 64 "w26.d0", "w26.d1", "w27.d0", "w27.d1", 65 "w28.d0", "w28.d1", "w29.d0", "w29.d1", 66 "w30.d0", "w30.d1", "w31.d0", "w31.d1", 67 }; 68 69 /* Encoding of Operation Field (must be indexed by CPUMIPSMSADataFormat) */ 70 struct dfe { 71 int start; 72 int length; 73 uint32_t mask; 74 }; 75 76 /* 77 * Extract immediate from df/{m,n} format (used by ELM & BIT instructions). 78 * Returns the immediate value, or -1 if the format does not match. 79 */ 80 static int df_extract_val(DisasContext *ctx, int x, const struct dfe *s) 81 { 82 for (unsigned i = 0; i < 4; i++) { 83 if (extract32(x, s->start, s->length) == s->mask) { 84 return extract32(x, 0, s->start); 85 } 86 } 87 return -1; 88 } 89 90 /* 91 * Extract DataField from df/{m,n} format (used by ELM & BIT instructions). 92 * Returns the DataField, or -1 if the format does not match. 93 */ 94 static int df_extract_df(DisasContext *ctx, int x, const struct dfe *s) 95 { 96 for (unsigned i = 0; i < 4; i++) { 97 if (extract32(x, s->start, s->length) == s->mask) { 98 return i; 99 } 100 } 101 return -1; 102 } 103 104 static const struct dfe df_elm[] = { 105 /* Table 3.26 ELM Instruction Format */ 106 [DF_BYTE] = {4, 2, 0b00}, 107 [DF_HALF] = {3, 3, 0b100}, 108 [DF_WORD] = {2, 4, 0b1100}, 109 [DF_DOUBLE] = {1, 5, 0b11100} 110 }; 111 112 static int elm_n(DisasContext *ctx, int x) 113 { 114 return df_extract_val(ctx, x, df_elm); 115 } 116 117 static int elm_df(DisasContext *ctx, int x) 118 { 119 return df_extract_df(ctx, x, df_elm); 120 } 121 122 static const struct dfe df_bit[] = { 123 /* Table 3.28 BIT Instruction Format */ 124 [DF_BYTE] = {3, 4, 0b1110}, 125 [DF_HALF] = {4, 3, 0b110}, 126 [DF_WORD] = {5, 2, 0b10}, 127 [DF_DOUBLE] = {6, 1, 0b0} 128 }; 129 130 static int bit_m(DisasContext *ctx, int x) 131 { 132 return df_extract_val(ctx, x, df_bit); 133 } 134 135 static int bit_df(DisasContext *ctx, int x) 136 { 137 return df_extract_df(ctx, x, df_bit); 138 } 139 140 static TCGv_i64 msa_wr_d[64]; 141 142 void msa_translate_init(void) 143 { 144 int i; 145 146 for (i = 0; i < 32; i++) { 147 int off; 148 149 /* 150 * The MSA vector registers are mapped on the 151 * scalar floating-point unit (FPU) registers. 152 */ 153 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); 154 msa_wr_d[i * 2] = fpu_f64[i]; 155 156 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); 157 msa_wr_d[i * 2 + 1] = 158 tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]); 159 } 160 } 161 162 /* 163 * Check if MSA is enabled. 164 * This function is always called with MSA available. 165 * If MSA is disabled, raise an exception. 166 */ 167 static inline bool check_msa_enabled(DisasContext *ctx) 168 { 169 if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && 170 !(ctx->hflags & MIPS_HFLAG_F64))) { 171 gen_reserved_instruction(ctx); 172 return false; 173 } 174 175 if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { 176 generate_exception_end(ctx, EXCP_MSADIS); 177 return false; 178 } 179 return true; 180 } 181 182 typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv); 183 typedef void gen_helper_pii(TCGv_ptr, TCGv_i32, TCGv_i32); 184 typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); 185 typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); 186 187 #define TRANS_DF_x(TYPE, NAME, trans_func, gen_func) \ 188 static gen_helper_p##TYPE * const NAME##_tab[4] = { \ 189 gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d \ 190 }; \ 191 TRANS(NAME, trans_func, NAME##_tab[a->df]) 192 193 #define TRANS_DF_iv(NAME, trans_func, gen_func) \ 194 TRANS_DF_x(iv, NAME, trans_func, gen_func) 195 196 #define TRANS_DF_ii(NAME, trans_func, gen_func) \ 197 TRANS_DF_x(ii, NAME, trans_func, gen_func) 198 199 #define TRANS_DF_iii(NAME, trans_func, gen_func) \ 200 TRANS_DF_x(iii, NAME, trans_func, gen_func) 201 202 #define TRANS_DF_iii_b(NAME, trans_func, gen_func) \ 203 static gen_helper_piii * const NAME##_tab[4] = { \ 204 NULL, gen_func##_h, gen_func##_w, gen_func##_d \ 205 }; \ 206 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 207 { \ 208 return trans_func(ctx, a, NAME##_tab[a->df]); \ 209 } 210 211 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, 212 TCGCond cond) 213 { 214 /* generates tcg ops to check if any element is 0 */ 215 /* Note this function only works with MSA_WRLEN = 128 */ 216 uint64_t eval_zero_or_big = dup_const(df, 1); 217 uint64_t eval_big = eval_zero_or_big << ((8 << df) - 1); 218 TCGv_i64 t0 = tcg_temp_new_i64(); 219 TCGv_i64 t1 = tcg_temp_new_i64(); 220 221 tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big); 222 tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]); 223 tcg_gen_andi_i64(t0, t0, eval_big); 224 tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big); 225 tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]); 226 tcg_gen_andi_i64(t1, t1, eval_big); 227 tcg_gen_or_i64(t0, t0, t1); 228 /* if all bits are zero then all elements are not zero */ 229 /* if some bit is non-zero then some element is zero */ 230 tcg_gen_setcondi_i64(cond, t0, t0, 0); 231 tcg_gen_trunc_i64_tl(tresult, t0); 232 tcg_temp_free_i64(t0); 233 tcg_temp_free_i64(t1); 234 } 235 236 static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond) 237 { 238 TCGv_i64 t0; 239 240 if (!check_msa_enabled(ctx)) { 241 return true; 242 } 243 244 if (ctx->hflags & MIPS_HFLAG_BMASK) { 245 gen_reserved_instruction(ctx); 246 return true; 247 } 248 t0 = tcg_temp_new_i64(); 249 tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); 250 tcg_gen_setcondi_i64(cond, t0, t0, 0); 251 tcg_gen_trunc_i64_tl(bcond, t0); 252 tcg_temp_free_i64(t0); 253 254 ctx->btarget = ctx->base.pc_next + (sa << 2) + 4; 255 256 ctx->hflags |= MIPS_HFLAG_BC; 257 ctx->hflags |= MIPS_HFLAG_BDS32; 258 259 return true; 260 } 261 262 static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a) 263 { 264 return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_EQ); 265 } 266 267 static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a) 268 { 269 return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_NE); 270 } 271 272 static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int sa, bool if_not) 273 { 274 if (!check_msa_enabled(ctx)) { 275 return true; 276 } 277 278 if (ctx->hflags & MIPS_HFLAG_BMASK) { 279 gen_reserved_instruction(ctx); 280 return true; 281 } 282 283 gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE); 284 285 ctx->btarget = ctx->base.pc_next + (sa << 2) + 4; 286 ctx->hflags |= MIPS_HFLAG_BC; 287 ctx->hflags |= MIPS_HFLAG_BDS32; 288 289 return true; 290 } 291 292 static bool trans_BZ(DisasContext *ctx, arg_msa_bz *a) 293 { 294 return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, false); 295 } 296 297 static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a) 298 { 299 return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true); 300 } 301 302 static bool trans_msa_i8(DisasContext *ctx, arg_msa_i *a, 303 gen_helper_piii *gen_msa_i8) 304 { 305 if (!check_msa_enabled(ctx)) { 306 return true; 307 } 308 309 gen_msa_i8(cpu_env, 310 tcg_constant_i32(a->wd), 311 tcg_constant_i32(a->ws), 312 tcg_constant_i32(a->sa)); 313 314 return true; 315 } 316 317 TRANS(ANDI, trans_msa_i8, gen_helper_msa_andi_b); 318 TRANS(ORI, trans_msa_i8, gen_helper_msa_ori_b); 319 TRANS(NORI, trans_msa_i8, gen_helper_msa_nori_b); 320 TRANS(XORI, trans_msa_i8, gen_helper_msa_xori_b); 321 TRANS(BMNZI, trans_msa_i8, gen_helper_msa_bmnzi_b); 322 TRANS(BMZI, trans_msa_i8, gen_helper_msa_bmzi_b); 323 TRANS(BSELI, trans_msa_i8, gen_helper_msa_bseli_b); 324 325 static bool trans_SHF(DisasContext *ctx, arg_msa_i *a) 326 { 327 if (a->df == DF_DOUBLE) { 328 return false; 329 } 330 331 if (!check_msa_enabled(ctx)) { 332 return true; 333 } 334 335 gen_helper_msa_shf_df(cpu_env, 336 tcg_constant_i32(a->df), 337 tcg_constant_i32(a->wd), 338 tcg_constant_i32(a->ws), 339 tcg_constant_i32(a->sa)); 340 341 return true; 342 } 343 344 static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *a, 345 gen_helper_piiii *gen_msa_i5) 346 { 347 if (!check_msa_enabled(ctx)) { 348 return true; 349 } 350 351 gen_msa_i5(cpu_env, 352 tcg_constant_i32(a->df), 353 tcg_constant_i32(a->wd), 354 tcg_constant_i32(a->ws), 355 tcg_constant_i32(a->sa)); 356 357 return true; 358 } 359 360 TRANS(ADDVI, trans_msa_i5, gen_helper_msa_addvi_df); 361 TRANS(SUBVI, trans_msa_i5, gen_helper_msa_subvi_df); 362 TRANS(MAXI_S, trans_msa_i5, gen_helper_msa_maxi_s_df); 363 TRANS(MAXI_U, trans_msa_i5, gen_helper_msa_maxi_u_df); 364 TRANS(MINI_S, trans_msa_i5, gen_helper_msa_mini_s_df); 365 TRANS(MINI_U, trans_msa_i5, gen_helper_msa_mini_u_df); 366 TRANS(CLTI_S, trans_msa_i5, gen_helper_msa_clti_s_df); 367 TRANS(CLTI_U, trans_msa_i5, gen_helper_msa_clti_u_df); 368 TRANS(CLEI_S, trans_msa_i5, gen_helper_msa_clei_s_df); 369 TRANS(CLEI_U, trans_msa_i5, gen_helper_msa_clei_u_df); 370 TRANS(CEQI, trans_msa_i5, gen_helper_msa_ceqi_df); 371 372 static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a) 373 { 374 if (!check_msa_enabled(ctx)) { 375 return true; 376 } 377 378 gen_helper_msa_ldi_df(cpu_env, 379 tcg_constant_i32(a->df), 380 tcg_constant_i32(a->wd), 381 tcg_constant_i32(a->sa)); 382 383 return true; 384 } 385 386 static bool trans_msa_bit(DisasContext *ctx, arg_msa_bit *a, 387 gen_helper_piiii *gen_msa_bit) 388 { 389 if (a->df < 0) { 390 return false; 391 } 392 393 if (!check_msa_enabled(ctx)) { 394 return true; 395 } 396 397 gen_msa_bit(cpu_env, 398 tcg_constant_i32(a->df), 399 tcg_constant_i32(a->wd), 400 tcg_constant_i32(a->ws), 401 tcg_constant_i32(a->m)); 402 403 return true; 404 } 405 406 TRANS(SLLI, trans_msa_bit, gen_helper_msa_slli_df); 407 TRANS(SRAI, trans_msa_bit, gen_helper_msa_srai_df); 408 TRANS(SRLI, trans_msa_bit, gen_helper_msa_srli_df); 409 TRANS(BCLRI, trans_msa_bit, gen_helper_msa_bclri_df); 410 TRANS(BSETI, trans_msa_bit, gen_helper_msa_bseti_df); 411 TRANS(BNEGI, trans_msa_bit, gen_helper_msa_bnegi_df); 412 TRANS(BINSLI, trans_msa_bit, gen_helper_msa_binsli_df); 413 TRANS(BINSRI, trans_msa_bit, gen_helper_msa_binsri_df); 414 TRANS(SAT_S, trans_msa_bit, gen_helper_msa_sat_u_df); 415 TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df); 416 TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df); 417 TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); 418 419 static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a, 420 gen_helper_piiii *gen_msa_3rf) 421 { 422 if (!check_msa_enabled(ctx)) { 423 return true; 424 } 425 426 gen_msa_3rf(cpu_env, 427 tcg_constant_i32(a->df), 428 tcg_constant_i32(a->wd), 429 tcg_constant_i32(a->ws), 430 tcg_constant_i32(a->wt)); 431 432 return true; 433 } 434 435 static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, 436 gen_helper_piii *gen_msa_3r) 437 { 438 if (!gen_msa_3r) { 439 return false; 440 } 441 442 if (!check_msa_enabled(ctx)) { 443 return true; 444 } 445 446 gen_msa_3r(cpu_env, 447 tcg_constant_i32(a->wd), 448 tcg_constant_i32(a->ws), 449 tcg_constant_i32(a->wt)); 450 451 return true; 452 } 453 454 TRANS(AND_V, trans_msa_3r, gen_helper_msa_and_v); 455 TRANS(OR_V, trans_msa_3r, gen_helper_msa_or_v); 456 TRANS(NOR_V, trans_msa_3r, gen_helper_msa_nor_v); 457 TRANS(XOR_V, trans_msa_3r, gen_helper_msa_xor_v); 458 TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v); 459 TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); 460 TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); 461 462 TRANS_DF_iii(SLL, trans_msa_3r, gen_helper_msa_sll); 463 TRANS_DF_iii(SRA, trans_msa_3r, gen_helper_msa_sra); 464 TRANS_DF_iii(SRL, trans_msa_3r, gen_helper_msa_srl); 465 TRANS_DF_iii(BCLR, trans_msa_3r, gen_helper_msa_bclr); 466 TRANS_DF_iii(BSET, trans_msa_3r, gen_helper_msa_bset); 467 TRANS_DF_iii(BNEG, trans_msa_3r, gen_helper_msa_bneg); 468 TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl); 469 TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr); 470 471 TRANS_DF_iii(ADDV, trans_msa_3r, gen_helper_msa_addv); 472 TRANS_DF_iii(SUBV, trans_msa_3r, gen_helper_msa_subv); 473 TRANS_DF_iii(MAX_S, trans_msa_3r, gen_helper_msa_max_s); 474 TRANS_DF_iii(MAX_U, trans_msa_3r, gen_helper_msa_max_u); 475 TRANS_DF_iii(MIN_S, trans_msa_3r, gen_helper_msa_min_s); 476 TRANS_DF_iii(MIN_U, trans_msa_3r, gen_helper_msa_min_u); 477 TRANS_DF_iii(MAX_A, trans_msa_3r, gen_helper_msa_max_a); 478 TRANS_DF_iii(MIN_A, trans_msa_3r, gen_helper_msa_min_a); 479 480 TRANS_DF_iii(CEQ, trans_msa_3r, gen_helper_msa_ceq); 481 TRANS_DF_iii(CLT_S, trans_msa_3r, gen_helper_msa_clt_s); 482 TRANS_DF_iii(CLT_U, trans_msa_3r, gen_helper_msa_clt_u); 483 TRANS_DF_iii(CLE_S, trans_msa_3r, gen_helper_msa_cle_s); 484 TRANS_DF_iii(CLE_U, trans_msa_3r, gen_helper_msa_cle_u); 485 486 TRANS_DF_iii(ADD_A, trans_msa_3r, gen_helper_msa_add_a); 487 TRANS_DF_iii(ADDS_A, trans_msa_3r, gen_helper_msa_adds_a); 488 TRANS_DF_iii(ADDS_S, trans_msa_3r, gen_helper_msa_adds_s); 489 TRANS_DF_iii(ADDS_U, trans_msa_3r, gen_helper_msa_adds_u); 490 TRANS_DF_iii(AVE_S, trans_msa_3r, gen_helper_msa_ave_s); 491 TRANS_DF_iii(AVE_U, trans_msa_3r, gen_helper_msa_ave_u); 492 TRANS_DF_iii(AVER_S, trans_msa_3r, gen_helper_msa_aver_s); 493 TRANS_DF_iii(AVER_U, trans_msa_3r, gen_helper_msa_aver_u); 494 495 TRANS_DF_iii(SUBS_S, trans_msa_3r, gen_helper_msa_subs_s); 496 TRANS_DF_iii(SUBS_U, trans_msa_3r, gen_helper_msa_subs_u); 497 TRANS_DF_iii(SUBSUS_U, trans_msa_3r, gen_helper_msa_subsus_u); 498 TRANS_DF_iii(SUBSUU_S, trans_msa_3r, gen_helper_msa_subsuu_s); 499 TRANS_DF_iii(ASUB_S, trans_msa_3r, gen_helper_msa_asub_s); 500 TRANS_DF_iii(ASUB_U, trans_msa_3r, gen_helper_msa_asub_u); 501 502 TRANS_DF_iii(MULV, trans_msa_3r, gen_helper_msa_mulv); 503 TRANS_DF_iii(MADDV, trans_msa_3r, gen_helper_msa_maddv); 504 TRANS_DF_iii(MSUBV, trans_msa_3r, gen_helper_msa_msubv); 505 TRANS_DF_iii(DIV_S, trans_msa_3r, gen_helper_msa_div_s); 506 TRANS_DF_iii(DIV_U, trans_msa_3r, gen_helper_msa_div_u); 507 TRANS_DF_iii(MOD_S, trans_msa_3r, gen_helper_msa_mod_s); 508 TRANS_DF_iii(MOD_U, trans_msa_3r, gen_helper_msa_mod_u); 509 510 TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s); 511 TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u); 512 TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s); 513 TRANS_DF_iii_b(DPADD_U, trans_msa_3r, gen_helper_msa_dpadd_u); 514 TRANS_DF_iii_b(DPSUB_S, trans_msa_3r, gen_helper_msa_dpsub_s); 515 TRANS_DF_iii_b(DPSUB_U, trans_msa_3r, gen_helper_msa_dpsub_u); 516 517 TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df); 518 TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df); 519 TRANS_DF_iii(PCKEV, trans_msa_3r, gen_helper_msa_pckev); 520 TRANS_DF_iii(PCKOD, trans_msa_3r, gen_helper_msa_pckod); 521 TRANS_DF_iii(ILVL, trans_msa_3r, gen_helper_msa_ilvl); 522 TRANS_DF_iii(ILVR, trans_msa_3r, gen_helper_msa_ilvr); 523 TRANS_DF_iii(ILVEV, trans_msa_3r, gen_helper_msa_ilvev); 524 TRANS_DF_iii(ILVOD, trans_msa_3r, gen_helper_msa_ilvod); 525 526 TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df); 527 TRANS_DF_iii(SRAR, trans_msa_3r, gen_helper_msa_srar); 528 TRANS_DF_iii(SRLR, trans_msa_3r, gen_helper_msa_srlr); 529 TRANS_DF_iii_b(HADD_S, trans_msa_3r, gen_helper_msa_hadd_s); 530 TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u); 531 TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s); 532 TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u); 533 534 static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a) 535 { 536 if (!check_msa_enabled(ctx)) { 537 return true; 538 } 539 540 gen_helper_msa_move_v(cpu_env, 541 tcg_constant_i32(a->wd), 542 tcg_constant_i32(a->ws)); 543 544 return true; 545 } 546 547 static void gen_msa_elm_3e(DisasContext *ctx) 548 { 549 #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) 550 uint8_t source = (ctx->opcode >> 11) & 0x1f; 551 uint8_t dest = (ctx->opcode >> 6) & 0x1f; 552 TCGv telm = tcg_temp_new(); 553 TCGv_i32 tdt = tcg_const_i32(dest); 554 555 switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { 556 case OPC_CTCMSA: 557 gen_load_gpr(telm, source); 558 gen_helper_msa_ctcmsa(cpu_env, telm, tdt); 559 break; 560 default: 561 MIPS_INVAL("MSA instruction"); 562 gen_reserved_instruction(ctx); 563 break; 564 } 565 566 tcg_temp_free(telm); 567 tcg_temp_free_i32(tdt); 568 } 569 570 static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a) 571 { 572 TCGv telm; 573 574 if (!check_msa_enabled(ctx)) { 575 return true; 576 } 577 578 telm = tcg_temp_new(); 579 580 gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws)); 581 gen_store_gpr(telm, a->wd); 582 583 tcg_temp_free(telm); 584 585 return true; 586 } 587 588 static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a, 589 gen_helper_piiii *gen_msa_elm_df) 590 { 591 if (a->df < 0) { 592 return false; 593 } 594 595 if (!check_msa_enabled(ctx)) { 596 return true; 597 } 598 599 gen_msa_elm_df(cpu_env, 600 tcg_constant_i32(a->df), 601 tcg_constant_i32(a->wd), 602 tcg_constant_i32(a->ws), 603 tcg_constant_i32(a->n)); 604 605 return true; 606 } 607 608 TRANS(SLDI, trans_msa_elm, gen_helper_msa_sldi_df); 609 TRANS(SPLATI, trans_msa_elm, gen_helper_msa_splati_df); 610 TRANS(INSVE, trans_msa_elm, gen_helper_msa_insve_df); 611 612 static bool trans_msa_elm_fn(DisasContext *ctx, arg_msa_elm_df *a, 613 gen_helper_piii * const gen_msa_elm[4]) 614 { 615 if (a->df < 0 || !gen_msa_elm[a->df]) { 616 return false; 617 } 618 619 if (check_msa_enabled(ctx)) { 620 return true; 621 } 622 623 if (a->wd == 0) { 624 /* Treat as NOP. */ 625 return true; 626 } 627 628 gen_msa_elm[a->df](cpu_env, 629 tcg_constant_i32(a->wd), 630 tcg_constant_i32(a->ws), 631 tcg_constant_i32(a->n)); 632 633 return true; 634 } 635 636 #if defined(TARGET_MIPS64) 637 #define NULL_IF_MIPS32(function) function 638 #else 639 #define NULL_IF_MIPS32(function) NULL 640 #endif 641 642 static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a) 643 { 644 static gen_helper_piii * const gen_msa_copy_u[4] = { 645 gen_helper_msa_copy_u_b, gen_helper_msa_copy_u_h, 646 NULL_IF_MIPS32(gen_helper_msa_copy_u_w), NULL 647 }; 648 649 return trans_msa_elm_fn(ctx, a, gen_msa_copy_u); 650 } 651 652 static bool trans_COPY_S(DisasContext *ctx, arg_msa_elm_df *a) 653 { 654 static gen_helper_piii * const gen_msa_copy_s[4] = { 655 gen_helper_msa_copy_s_b, gen_helper_msa_copy_s_h, 656 gen_helper_msa_copy_s_w, NULL_IF_MIPS32(gen_helper_msa_copy_s_d) 657 }; 658 659 return trans_msa_elm_fn(ctx, a, gen_msa_copy_s); 660 } 661 662 static bool trans_INSERT(DisasContext *ctx, arg_msa_elm_df *a) 663 { 664 static gen_helper_piii * const gen_msa_insert[4] = { 665 gen_helper_msa_insert_b, gen_helper_msa_insert_h, 666 gen_helper_msa_insert_w, NULL_IF_MIPS32(gen_helper_msa_insert_d) 667 }; 668 669 return trans_msa_elm_fn(ctx, a, gen_msa_insert); 670 } 671 672 static void gen_msa_elm(DisasContext *ctx) 673 { 674 uint8_t dfn = (ctx->opcode >> 16) & 0x3f; 675 676 if (dfn == 0x3E) { 677 /* CTCMSA */ 678 gen_msa_elm_3e(ctx); 679 return; 680 } else { 681 gen_reserved_instruction(ctx); 682 return; 683 } 684 } 685 686 TRANS(FCAF, trans_msa_3rf, gen_helper_msa_fcaf_df); 687 TRANS(FCUN, trans_msa_3rf, gen_helper_msa_fcun_df); 688 TRANS(FCEQ, trans_msa_3rf, gen_helper_msa_fceq_df); 689 TRANS(FCUEQ, trans_msa_3rf, gen_helper_msa_fcueq_df); 690 TRANS(FCLT, trans_msa_3rf, gen_helper_msa_fclt_df); 691 TRANS(FCULT, trans_msa_3rf, gen_helper_msa_fcult_df); 692 TRANS(FCLE, trans_msa_3rf, gen_helper_msa_fcle_df); 693 TRANS(FCULE, trans_msa_3rf, gen_helper_msa_fcule_df); 694 TRANS(FSAF, trans_msa_3rf, gen_helper_msa_fsaf_df); 695 TRANS(FSUN, trans_msa_3rf, gen_helper_msa_fsun_df); 696 TRANS(FSEQ, trans_msa_3rf, gen_helper_msa_fseq_df); 697 TRANS(FSUEQ, trans_msa_3rf, gen_helper_msa_fsueq_df); 698 TRANS(FSLT, trans_msa_3rf, gen_helper_msa_fslt_df); 699 TRANS(FSULT, trans_msa_3rf, gen_helper_msa_fsult_df); 700 TRANS(FSLE, trans_msa_3rf, gen_helper_msa_fsle_df); 701 TRANS(FSULE, trans_msa_3rf, gen_helper_msa_fsule_df); 702 703 TRANS(FADD, trans_msa_3rf, gen_helper_msa_fadd_df); 704 TRANS(FSUB, trans_msa_3rf, gen_helper_msa_fsub_df); 705 TRANS(FMUL, trans_msa_3rf, gen_helper_msa_fmul_df); 706 TRANS(FDIV, trans_msa_3rf, gen_helper_msa_fdiv_df); 707 TRANS(FMADD, trans_msa_3rf, gen_helper_msa_fmadd_df); 708 TRANS(FMSUB, trans_msa_3rf, gen_helper_msa_fmsub_df); 709 TRANS(FEXP2, trans_msa_3rf, gen_helper_msa_fexp2_df); 710 TRANS(FEXDO, trans_msa_3rf, gen_helper_msa_fexdo_df); 711 TRANS(FTQ, trans_msa_3rf, gen_helper_msa_ftq_df); 712 TRANS(FMIN, trans_msa_3rf, gen_helper_msa_fmin_df); 713 TRANS(FMIN_A, trans_msa_3rf, gen_helper_msa_fmin_a_df); 714 TRANS(FMAX, trans_msa_3rf, gen_helper_msa_fmax_df); 715 TRANS(FMAX_A, trans_msa_3rf, gen_helper_msa_fmax_a_df); 716 717 TRANS(FCOR, trans_msa_3rf, gen_helper_msa_fcor_df); 718 TRANS(FCUNE, trans_msa_3rf, gen_helper_msa_fcune_df); 719 TRANS(FCNE, trans_msa_3rf, gen_helper_msa_fcne_df); 720 TRANS(MUL_Q, trans_msa_3rf, gen_helper_msa_mul_q_df); 721 TRANS(MADD_Q, trans_msa_3rf, gen_helper_msa_madd_q_df); 722 TRANS(MSUB_Q, trans_msa_3rf, gen_helper_msa_msub_q_df); 723 TRANS(FSOR, trans_msa_3rf, gen_helper_msa_fsor_df); 724 TRANS(FSUNE, trans_msa_3rf, gen_helper_msa_fsune_df); 725 TRANS(FSNE, trans_msa_3rf, gen_helper_msa_fsne_df); 726 TRANS(MULR_Q, trans_msa_3rf, gen_helper_msa_mulr_q_df); 727 TRANS(MADDR_Q, trans_msa_3rf, gen_helper_msa_maddr_q_df); 728 TRANS(MSUBR_Q, trans_msa_3rf, gen_helper_msa_msubr_q_df); 729 730 static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a, 731 gen_helper_pii *gen_msa_2r) 732 { 733 if (!check_msa_enabled(ctx)) { 734 return true; 735 } 736 737 gen_msa_2r(cpu_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws)); 738 739 return true; 740 } 741 742 TRANS_DF_ii(PCNT, trans_msa_2r, gen_helper_msa_pcnt); 743 TRANS_DF_ii(NLOC, trans_msa_2r, gen_helper_msa_nloc); 744 TRANS_DF_ii(NLZC, trans_msa_2r, gen_helper_msa_nlzc); 745 746 static bool trans_FILL(DisasContext *ctx, arg_msa_r *a) 747 { 748 if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) { 749 /* Double format valid only for MIPS64 */ 750 return false; 751 } 752 753 if (!check_msa_enabled(ctx)) { 754 return true; 755 } 756 757 gen_helper_msa_fill_df(cpu_env, 758 tcg_constant_i32(a->df), 759 tcg_constant_i32(a->wd), 760 tcg_constant_i32(a->ws)); 761 762 return true; 763 } 764 765 static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a, 766 gen_helper_piii *gen_msa_2rf) 767 { 768 if (!check_msa_enabled(ctx)) { 769 return true; 770 } 771 772 gen_msa_2rf(cpu_env, 773 tcg_constant_i32(a->df), 774 tcg_constant_i32(a->wd), 775 tcg_constant_i32(a->ws)); 776 777 return true; 778 } 779 780 TRANS(FCLASS, trans_msa_2rf, gen_helper_msa_fclass_df); 781 TRANS(FTRUNC_S, trans_msa_2rf, gen_helper_msa_fclass_df); 782 TRANS(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_s_df); 783 TRANS(FSQRT, trans_msa_2rf, gen_helper_msa_fsqrt_df); 784 TRANS(FRSQRT, trans_msa_2rf, gen_helper_msa_frsqrt_df); 785 TRANS(FRCP, trans_msa_2rf, gen_helper_msa_frcp_df); 786 TRANS(FRINT, trans_msa_2rf, gen_helper_msa_frint_df); 787 TRANS(FLOG2, trans_msa_2rf, gen_helper_msa_flog2_df); 788 TRANS(FEXUPL, trans_msa_2rf, gen_helper_msa_fexupl_df); 789 TRANS(FEXUPR, trans_msa_2rf, gen_helper_msa_fexupr_df); 790 TRANS(FFQL, trans_msa_2rf, gen_helper_msa_ffql_df); 791 TRANS(FFQR, trans_msa_2rf, gen_helper_msa_ffqr_df); 792 TRANS(FTINT_S, trans_msa_2rf, gen_helper_msa_ftint_s_df); 793 TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df); 794 TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); 795 TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); 796 797 static bool trans_MSA(DisasContext *ctx, arg_MSA *a) 798 { 799 uint32_t opcode = ctx->opcode; 800 801 if (!check_msa_enabled(ctx)) { 802 return true; 803 } 804 805 switch (MASK_MSA_MINOR(opcode)) { 806 case OPC_MSA_ELM: 807 gen_msa_elm(ctx); 808 break; 809 default: 810 MIPS_INVAL("MSA instruction"); 811 gen_reserved_instruction(ctx); 812 break; 813 } 814 815 return true; 816 } 817 818 static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, 819 gen_helper_piv *gen_msa_ldst) 820 { 821 TCGv taddr; 822 823 if (!check_msa_enabled(ctx)) { 824 return true; 825 } 826 827 taddr = tcg_temp_new(); 828 829 gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df); 830 gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr); 831 832 tcg_temp_free(taddr); 833 834 return true; 835 } 836 837 TRANS_DF_iv(LD, trans_msa_ldst, gen_helper_msa_ld); 838 TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st); 839 840 static bool trans_LSA(DisasContext *ctx, arg_r *a) 841 { 842 return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); 843 } 844 845 static bool trans_DLSA(DisasContext *ctx, arg_r *a) 846 { 847 if (TARGET_LONG_BITS != 64) { 848 return false; 849 } 850 return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); 851 } 852