1 /* 2 * MIPS SIMD Architecture (MSA) translation routines 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * Copyright (c) 2006 Marius Groeger (FPU operations) 6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) 7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) 8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) 9 * Copyright (c) 2020 Philippe Mathieu-Daudé 10 * 11 * SPDX-License-Identifier: LGPL-2.1-or-later 12 */ 13 #include "qemu/osdep.h" 14 #include "tcg/tcg-op.h" 15 #include "exec/helper-gen.h" 16 #include "translate.h" 17 #include "fpu_helper.h" 18 #include "internal.h" 19 20 static int elm_n(DisasContext *ctx, int x); 21 static int elm_df(DisasContext *ctx, int x); 22 static int bit_m(DisasContext *ctx, int x); 23 static int bit_df(DisasContext *ctx, int x); 24 25 static inline int plus_1(DisasContext *s, int x) 26 { 27 return x + 1; 28 } 29 30 static inline int plus_2(DisasContext *s, int x) 31 { 32 return x + 2; 33 } 34 35 /* Include the auto-generated decoder. */ 36 #include "decode-msa.c.inc" 37 38 #define OPC_MSA (0x1E << 26) 39 40 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 41 enum { 42 OPC_MSA_ELM = 0x19 | OPC_MSA, 43 }; 44 45 enum { 46 /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */ 47 OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, 48 OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, 49 }; 50 51 static const char msaregnames[][6] = { 52 "w0.d0", "w0.d1", "w1.d0", "w1.d1", 53 "w2.d0", "w2.d1", "w3.d0", "w3.d1", 54 "w4.d0", "w4.d1", "w5.d0", "w5.d1", 55 "w6.d0", "w6.d1", "w7.d0", "w7.d1", 56 "w8.d0", "w8.d1", "w9.d0", "w9.d1", 57 "w10.d0", "w10.d1", "w11.d0", "w11.d1", 58 "w12.d0", "w12.d1", "w13.d0", "w13.d1", 59 "w14.d0", "w14.d1", "w15.d0", "w15.d1", 60 "w16.d0", "w16.d1", "w17.d0", "w17.d1", 61 "w18.d0", "w18.d1", "w19.d0", "w19.d1", 62 "w20.d0", "w20.d1", "w21.d0", "w21.d1", 63 "w22.d0", "w22.d1", "w23.d0", "w23.d1", 64 "w24.d0", "w24.d1", "w25.d0", "w25.d1", 65 "w26.d0", "w26.d1", "w27.d0", "w27.d1", 66 "w28.d0", "w28.d1", "w29.d0", "w29.d1", 67 "w30.d0", "w30.d1", "w31.d0", "w31.d1", 68 }; 69 70 /* Encoding of Operation Field (must be indexed by CPUMIPSMSADataFormat) */ 71 struct dfe { 72 int start; 73 int length; 74 uint32_t mask; 75 }; 76 77 /* 78 * Extract immediate from df/{m,n} format (used by ELM & BIT instructions). 79 * Returns the immediate value, or -1 if the format does not match. 80 */ 81 static int df_extract_val(DisasContext *ctx, int x, const struct dfe *s) 82 { 83 for (unsigned i = 0; i < 4; i++) { 84 if (extract32(x, s->start, s->length) == s->mask) { 85 return extract32(x, 0, s->start); 86 } 87 } 88 return -1; 89 } 90 91 /* 92 * Extract DataField from df/{m,n} format (used by ELM & BIT instructions). 93 * Returns the DataField, or -1 if the format does not match. 94 */ 95 static int df_extract_df(DisasContext *ctx, int x, const struct dfe *s) 96 { 97 for (unsigned i = 0; i < 4; i++) { 98 if (extract32(x, s->start, s->length) == s->mask) { 99 return i; 100 } 101 } 102 return -1; 103 } 104 105 static const struct dfe df_elm[] = { 106 /* Table 3.26 ELM Instruction Format */ 107 [DF_BYTE] = {4, 2, 0b00}, 108 [DF_HALF] = {3, 3, 0b100}, 109 [DF_WORD] = {2, 4, 0b1100}, 110 [DF_DOUBLE] = {1, 5, 0b11100} 111 }; 112 113 static int elm_n(DisasContext *ctx, int x) 114 { 115 return df_extract_val(ctx, x, df_elm); 116 } 117 118 static int elm_df(DisasContext *ctx, int x) 119 { 120 return df_extract_df(ctx, x, df_elm); 121 } 122 123 static const struct dfe df_bit[] = { 124 /* Table 3.28 BIT Instruction Format */ 125 [DF_BYTE] = {3, 4, 0b1110}, 126 [DF_HALF] = {4, 3, 0b110}, 127 [DF_WORD] = {5, 2, 0b10}, 128 [DF_DOUBLE] = {6, 1, 0b0} 129 }; 130 131 static int bit_m(DisasContext *ctx, int x) 132 { 133 return df_extract_val(ctx, x, df_bit); 134 } 135 136 static int bit_df(DisasContext *ctx, int x) 137 { 138 return df_extract_df(ctx, x, df_bit); 139 } 140 141 static TCGv_i64 msa_wr_d[64]; 142 143 void msa_translate_init(void) 144 { 145 int i; 146 147 for (i = 0; i < 32; i++) { 148 int off; 149 150 /* 151 * The MSA vector registers are mapped on the 152 * scalar floating-point unit (FPU) registers. 153 */ 154 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); 155 msa_wr_d[i * 2] = fpu_f64[i]; 156 157 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); 158 msa_wr_d[i * 2 + 1] = 159 tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]); 160 } 161 } 162 163 /* 164 * Check if MSA is enabled. 165 * This function is always called with MSA available. 166 * If MSA is disabled, raise an exception. 167 */ 168 static inline bool check_msa_enabled(DisasContext *ctx) 169 { 170 if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && 171 !(ctx->hflags & MIPS_HFLAG_F64))) { 172 gen_reserved_instruction(ctx); 173 return false; 174 } 175 176 if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { 177 generate_exception_end(ctx, EXCP_MSADIS); 178 return false; 179 } 180 return true; 181 } 182 183 typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv); 184 typedef void gen_helper_pii(TCGv_ptr, TCGv_i32, TCGv_i32); 185 typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); 186 typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); 187 188 #define TRANS_DF_x(TYPE, NAME, trans_func, gen_func) \ 189 static gen_helper_p##TYPE * const NAME##_tab[4] = { \ 190 gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d \ 191 }; \ 192 TRANS(NAME, trans_func, NAME##_tab[a->df]) 193 194 #define TRANS_DF_iv(NAME, trans_func, gen_func) \ 195 TRANS_DF_x(iv, NAME, trans_func, gen_func) 196 197 #define TRANS_DF_ii(NAME, trans_func, gen_func) \ 198 TRANS_DF_x(ii, NAME, trans_func, gen_func) 199 200 #define TRANS_DF_iii(NAME, trans_func, gen_func) \ 201 TRANS_DF_x(iii, NAME, trans_func, gen_func) 202 203 #define TRANS_DF_iii_b(NAME, trans_func, gen_func) \ 204 static gen_helper_piii * const NAME##_tab[4] = { \ 205 NULL, gen_func##_h, gen_func##_w, gen_func##_d \ 206 }; \ 207 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 208 { \ 209 return trans_func(ctx, a, NAME##_tab[a->df]); \ 210 } 211 212 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, 213 TCGCond cond) 214 { 215 /* generates tcg ops to check if any element is 0 */ 216 /* Note this function only works with MSA_WRLEN = 128 */ 217 uint64_t eval_zero_or_big = dup_const(df, 1); 218 uint64_t eval_big = eval_zero_or_big << ((8 << df) - 1); 219 TCGv_i64 t0 = tcg_temp_new_i64(); 220 TCGv_i64 t1 = tcg_temp_new_i64(); 221 222 tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big); 223 tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]); 224 tcg_gen_andi_i64(t0, t0, eval_big); 225 tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big); 226 tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]); 227 tcg_gen_andi_i64(t1, t1, eval_big); 228 tcg_gen_or_i64(t0, t0, t1); 229 /* if all bits are zero then all elements are not zero */ 230 /* if some bit is non-zero then some element is zero */ 231 tcg_gen_setcondi_i64(cond, t0, t0, 0); 232 tcg_gen_trunc_i64_tl(tresult, t0); 233 tcg_temp_free_i64(t0); 234 tcg_temp_free_i64(t1); 235 } 236 237 static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond) 238 { 239 TCGv_i64 t0; 240 241 if (!check_msa_enabled(ctx)) { 242 return true; 243 } 244 245 if (ctx->hflags & MIPS_HFLAG_BMASK) { 246 gen_reserved_instruction(ctx); 247 return true; 248 } 249 t0 = tcg_temp_new_i64(); 250 tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); 251 tcg_gen_setcondi_i64(cond, t0, t0, 0); 252 tcg_gen_trunc_i64_tl(bcond, t0); 253 tcg_temp_free_i64(t0); 254 255 ctx->btarget = ctx->base.pc_next + (sa << 2) + 4; 256 257 ctx->hflags |= MIPS_HFLAG_BC; 258 ctx->hflags |= MIPS_HFLAG_BDS32; 259 260 return true; 261 } 262 263 static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a) 264 { 265 return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_EQ); 266 } 267 268 static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a) 269 { 270 return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_NE); 271 } 272 273 static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int sa, bool if_not) 274 { 275 if (!check_msa_enabled(ctx)) { 276 return true; 277 } 278 279 if (ctx->hflags & MIPS_HFLAG_BMASK) { 280 gen_reserved_instruction(ctx); 281 return true; 282 } 283 284 gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE); 285 286 ctx->btarget = ctx->base.pc_next + (sa << 2) + 4; 287 ctx->hflags |= MIPS_HFLAG_BC; 288 ctx->hflags |= MIPS_HFLAG_BDS32; 289 290 return true; 291 } 292 293 static bool trans_BZ(DisasContext *ctx, arg_msa_bz *a) 294 { 295 return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, false); 296 } 297 298 static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a) 299 { 300 return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true); 301 } 302 303 static bool trans_msa_i8(DisasContext *ctx, arg_msa_i *a, 304 gen_helper_piii *gen_msa_i8) 305 { 306 if (!check_msa_enabled(ctx)) { 307 return true; 308 } 309 310 gen_msa_i8(cpu_env, 311 tcg_constant_i32(a->wd), 312 tcg_constant_i32(a->ws), 313 tcg_constant_i32(a->sa)); 314 315 return true; 316 } 317 318 TRANS(ANDI, trans_msa_i8, gen_helper_msa_andi_b); 319 TRANS(ORI, trans_msa_i8, gen_helper_msa_ori_b); 320 TRANS(NORI, trans_msa_i8, gen_helper_msa_nori_b); 321 TRANS(XORI, trans_msa_i8, gen_helper_msa_xori_b); 322 TRANS(BMNZI, trans_msa_i8, gen_helper_msa_bmnzi_b); 323 TRANS(BMZI, trans_msa_i8, gen_helper_msa_bmzi_b); 324 TRANS(BSELI, trans_msa_i8, gen_helper_msa_bseli_b); 325 326 static bool trans_SHF(DisasContext *ctx, arg_msa_i *a) 327 { 328 if (a->df == DF_DOUBLE) { 329 return false; 330 } 331 332 if (!check_msa_enabled(ctx)) { 333 return true; 334 } 335 336 gen_helper_msa_shf_df(cpu_env, 337 tcg_constant_i32(a->df), 338 tcg_constant_i32(a->wd), 339 tcg_constant_i32(a->ws), 340 tcg_constant_i32(a->sa)); 341 342 return true; 343 } 344 345 static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *a, 346 gen_helper_piiii *gen_msa_i5) 347 { 348 if (!check_msa_enabled(ctx)) { 349 return true; 350 } 351 352 gen_msa_i5(cpu_env, 353 tcg_constant_i32(a->df), 354 tcg_constant_i32(a->wd), 355 tcg_constant_i32(a->ws), 356 tcg_constant_i32(a->sa)); 357 358 return true; 359 } 360 361 TRANS(ADDVI, trans_msa_i5, gen_helper_msa_addvi_df); 362 TRANS(SUBVI, trans_msa_i5, gen_helper_msa_subvi_df); 363 TRANS(MAXI_S, trans_msa_i5, gen_helper_msa_maxi_s_df); 364 TRANS(MAXI_U, trans_msa_i5, gen_helper_msa_maxi_u_df); 365 TRANS(MINI_S, trans_msa_i5, gen_helper_msa_mini_s_df); 366 TRANS(MINI_U, trans_msa_i5, gen_helper_msa_mini_u_df); 367 TRANS(CLTI_S, trans_msa_i5, gen_helper_msa_clti_s_df); 368 TRANS(CLTI_U, trans_msa_i5, gen_helper_msa_clti_u_df); 369 TRANS(CLEI_S, trans_msa_i5, gen_helper_msa_clei_s_df); 370 TRANS(CLEI_U, trans_msa_i5, gen_helper_msa_clei_u_df); 371 TRANS(CEQI, trans_msa_i5, gen_helper_msa_ceqi_df); 372 373 static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a) 374 { 375 if (!check_msa_enabled(ctx)) { 376 return true; 377 } 378 379 gen_helper_msa_ldi_df(cpu_env, 380 tcg_constant_i32(a->df), 381 tcg_constant_i32(a->wd), 382 tcg_constant_i32(a->sa)); 383 384 return true; 385 } 386 387 static bool trans_msa_bit(DisasContext *ctx, arg_msa_bit *a, 388 gen_helper_piiii *gen_msa_bit) 389 { 390 if (a->df < 0) { 391 return false; 392 } 393 394 if (!check_msa_enabled(ctx)) { 395 return true; 396 } 397 398 gen_msa_bit(cpu_env, 399 tcg_constant_i32(a->df), 400 tcg_constant_i32(a->wd), 401 tcg_constant_i32(a->ws), 402 tcg_constant_i32(a->m)); 403 404 return true; 405 } 406 407 TRANS(SLLI, trans_msa_bit, gen_helper_msa_slli_df); 408 TRANS(SRAI, trans_msa_bit, gen_helper_msa_srai_df); 409 TRANS(SRLI, trans_msa_bit, gen_helper_msa_srli_df); 410 TRANS(BCLRI, trans_msa_bit, gen_helper_msa_bclri_df); 411 TRANS(BSETI, trans_msa_bit, gen_helper_msa_bseti_df); 412 TRANS(BNEGI, trans_msa_bit, gen_helper_msa_bnegi_df); 413 TRANS(BINSLI, trans_msa_bit, gen_helper_msa_binsli_df); 414 TRANS(BINSRI, trans_msa_bit, gen_helper_msa_binsri_df); 415 TRANS(SAT_S, trans_msa_bit, gen_helper_msa_sat_u_df); 416 TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df); 417 TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df); 418 TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); 419 420 static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a, 421 gen_helper_piiii *gen_msa_3rf) 422 { 423 if (!check_msa_enabled(ctx)) { 424 return true; 425 } 426 427 gen_msa_3rf(cpu_env, 428 tcg_constant_i32(a->df), 429 tcg_constant_i32(a->wd), 430 tcg_constant_i32(a->ws), 431 tcg_constant_i32(a->wt)); 432 433 return true; 434 } 435 436 static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, 437 gen_helper_piii *gen_msa_3r) 438 { 439 if (!gen_msa_3r) { 440 return false; 441 } 442 443 if (!check_msa_enabled(ctx)) { 444 return true; 445 } 446 447 gen_msa_3r(cpu_env, 448 tcg_constant_i32(a->wd), 449 tcg_constant_i32(a->ws), 450 tcg_constant_i32(a->wt)); 451 452 return true; 453 } 454 455 TRANS(AND_V, trans_msa_3r, gen_helper_msa_and_v); 456 TRANS(OR_V, trans_msa_3r, gen_helper_msa_or_v); 457 TRANS(NOR_V, trans_msa_3r, gen_helper_msa_nor_v); 458 TRANS(XOR_V, trans_msa_3r, gen_helper_msa_xor_v); 459 TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v); 460 TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); 461 TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); 462 463 TRANS_DF_iii(SLL, trans_msa_3r, gen_helper_msa_sll); 464 TRANS_DF_iii(SRA, trans_msa_3r, gen_helper_msa_sra); 465 TRANS_DF_iii(SRL, trans_msa_3r, gen_helper_msa_srl); 466 TRANS_DF_iii(BCLR, trans_msa_3r, gen_helper_msa_bclr); 467 TRANS_DF_iii(BSET, trans_msa_3r, gen_helper_msa_bset); 468 TRANS_DF_iii(BNEG, trans_msa_3r, gen_helper_msa_bneg); 469 TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl); 470 TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr); 471 472 TRANS_DF_iii(ADDV, trans_msa_3r, gen_helper_msa_addv); 473 TRANS_DF_iii(SUBV, trans_msa_3r, gen_helper_msa_subv); 474 TRANS_DF_iii(MAX_S, trans_msa_3r, gen_helper_msa_max_s); 475 TRANS_DF_iii(MAX_U, trans_msa_3r, gen_helper_msa_max_u); 476 TRANS_DF_iii(MIN_S, trans_msa_3r, gen_helper_msa_min_s); 477 TRANS_DF_iii(MIN_U, trans_msa_3r, gen_helper_msa_min_u); 478 TRANS_DF_iii(MAX_A, trans_msa_3r, gen_helper_msa_max_a); 479 TRANS_DF_iii(MIN_A, trans_msa_3r, gen_helper_msa_min_a); 480 481 TRANS_DF_iii(CEQ, trans_msa_3r, gen_helper_msa_ceq); 482 TRANS_DF_iii(CLT_S, trans_msa_3r, gen_helper_msa_clt_s); 483 TRANS_DF_iii(CLT_U, trans_msa_3r, gen_helper_msa_clt_u); 484 TRANS_DF_iii(CLE_S, trans_msa_3r, gen_helper_msa_cle_s); 485 TRANS_DF_iii(CLE_U, trans_msa_3r, gen_helper_msa_cle_u); 486 487 TRANS_DF_iii(ADD_A, trans_msa_3r, gen_helper_msa_add_a); 488 TRANS_DF_iii(ADDS_A, trans_msa_3r, gen_helper_msa_adds_a); 489 TRANS_DF_iii(ADDS_S, trans_msa_3r, gen_helper_msa_adds_s); 490 TRANS_DF_iii(ADDS_U, trans_msa_3r, gen_helper_msa_adds_u); 491 TRANS_DF_iii(AVE_S, trans_msa_3r, gen_helper_msa_ave_s); 492 TRANS_DF_iii(AVE_U, trans_msa_3r, gen_helper_msa_ave_u); 493 TRANS_DF_iii(AVER_S, trans_msa_3r, gen_helper_msa_aver_s); 494 TRANS_DF_iii(AVER_U, trans_msa_3r, gen_helper_msa_aver_u); 495 496 TRANS_DF_iii(SUBS_S, trans_msa_3r, gen_helper_msa_subs_s); 497 TRANS_DF_iii(SUBS_U, trans_msa_3r, gen_helper_msa_subs_u); 498 TRANS_DF_iii(SUBSUS_U, trans_msa_3r, gen_helper_msa_subsus_u); 499 TRANS_DF_iii(SUBSUU_S, trans_msa_3r, gen_helper_msa_subsuu_s); 500 TRANS_DF_iii(ASUB_S, trans_msa_3r, gen_helper_msa_asub_s); 501 TRANS_DF_iii(ASUB_U, trans_msa_3r, gen_helper_msa_asub_u); 502 503 TRANS_DF_iii(MULV, trans_msa_3r, gen_helper_msa_mulv); 504 TRANS_DF_iii(MADDV, trans_msa_3r, gen_helper_msa_maddv); 505 TRANS_DF_iii(MSUBV, trans_msa_3r, gen_helper_msa_msubv); 506 TRANS_DF_iii(DIV_S, trans_msa_3r, gen_helper_msa_div_s); 507 TRANS_DF_iii(DIV_U, trans_msa_3r, gen_helper_msa_div_u); 508 TRANS_DF_iii(MOD_S, trans_msa_3r, gen_helper_msa_mod_s); 509 TRANS_DF_iii(MOD_U, trans_msa_3r, gen_helper_msa_mod_u); 510 511 TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s); 512 TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u); 513 TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s); 514 TRANS_DF_iii_b(DPADD_U, trans_msa_3r, gen_helper_msa_dpadd_u); 515 TRANS_DF_iii_b(DPSUB_S, trans_msa_3r, gen_helper_msa_dpsub_s); 516 TRANS_DF_iii_b(DPSUB_U, trans_msa_3r, gen_helper_msa_dpsub_u); 517 518 TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df); 519 TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df); 520 TRANS_DF_iii(PCKEV, trans_msa_3r, gen_helper_msa_pckev); 521 TRANS_DF_iii(PCKOD, trans_msa_3r, gen_helper_msa_pckod); 522 TRANS_DF_iii(ILVL, trans_msa_3r, gen_helper_msa_ilvl); 523 TRANS_DF_iii(ILVR, trans_msa_3r, gen_helper_msa_ilvr); 524 TRANS_DF_iii(ILVEV, trans_msa_3r, gen_helper_msa_ilvev); 525 TRANS_DF_iii(ILVOD, trans_msa_3r, gen_helper_msa_ilvod); 526 527 TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df); 528 TRANS_DF_iii(SRAR, trans_msa_3r, gen_helper_msa_srar); 529 TRANS_DF_iii(SRLR, trans_msa_3r, gen_helper_msa_srlr); 530 TRANS_DF_iii_b(HADD_S, trans_msa_3r, gen_helper_msa_hadd_s); 531 TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u); 532 TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s); 533 TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u); 534 535 static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a) 536 { 537 if (!check_msa_enabled(ctx)) { 538 return true; 539 } 540 541 gen_helper_msa_move_v(cpu_env, 542 tcg_constant_i32(a->wd), 543 tcg_constant_i32(a->ws)); 544 545 return true; 546 } 547 548 static void gen_msa_elm_3e(DisasContext *ctx) 549 { 550 #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) 551 uint8_t source = (ctx->opcode >> 11) & 0x1f; 552 uint8_t dest = (ctx->opcode >> 6) & 0x1f; 553 TCGv telm = tcg_temp_new(); 554 TCGv_i32 tsr = tcg_const_i32(source); 555 TCGv_i32 tdt = tcg_const_i32(dest); 556 557 switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { 558 case OPC_CTCMSA: 559 gen_load_gpr(telm, source); 560 gen_helper_msa_ctcmsa(cpu_env, telm, tdt); 561 break; 562 case OPC_CFCMSA: 563 gen_helper_msa_cfcmsa(telm, cpu_env, tsr); 564 gen_store_gpr(telm, dest); 565 break; 566 default: 567 MIPS_INVAL("MSA instruction"); 568 gen_reserved_instruction(ctx); 569 break; 570 } 571 572 tcg_temp_free(telm); 573 tcg_temp_free_i32(tdt); 574 tcg_temp_free_i32(tsr); 575 } 576 577 static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a, 578 gen_helper_piiii *gen_msa_elm_df) 579 { 580 if (a->df < 0) { 581 return false; 582 } 583 584 if (!check_msa_enabled(ctx)) { 585 return true; 586 } 587 588 gen_msa_elm_df(cpu_env, 589 tcg_constant_i32(a->df), 590 tcg_constant_i32(a->wd), 591 tcg_constant_i32(a->ws), 592 tcg_constant_i32(a->n)); 593 594 return true; 595 } 596 597 TRANS(SLDI, trans_msa_elm, gen_helper_msa_sldi_df); 598 TRANS(SPLATI, trans_msa_elm, gen_helper_msa_splati_df); 599 TRANS(INSVE, trans_msa_elm, gen_helper_msa_insve_df); 600 601 static bool trans_msa_elm_fn(DisasContext *ctx, arg_msa_elm_df *a, 602 gen_helper_piii * const gen_msa_elm[4]) 603 { 604 if (a->df < 0 || !gen_msa_elm[a->df]) { 605 return false; 606 } 607 608 if (check_msa_enabled(ctx)) { 609 return true; 610 } 611 612 if (a->wd == 0) { 613 /* Treat as NOP. */ 614 return true; 615 } 616 617 gen_msa_elm[a->df](cpu_env, 618 tcg_constant_i32(a->wd), 619 tcg_constant_i32(a->ws), 620 tcg_constant_i32(a->n)); 621 622 return true; 623 } 624 625 #if defined(TARGET_MIPS64) 626 #define NULL_IF_MIPS32(function) function 627 #else 628 #define NULL_IF_MIPS32(function) NULL 629 #endif 630 631 static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a) 632 { 633 static gen_helper_piii * const gen_msa_copy_u[4] = { 634 gen_helper_msa_copy_u_b, gen_helper_msa_copy_u_h, 635 NULL_IF_MIPS32(gen_helper_msa_copy_u_w), NULL 636 }; 637 638 return trans_msa_elm_fn(ctx, a, gen_msa_copy_u); 639 } 640 641 static bool trans_COPY_S(DisasContext *ctx, arg_msa_elm_df *a) 642 { 643 static gen_helper_piii * const gen_msa_copy_s[4] = { 644 gen_helper_msa_copy_s_b, gen_helper_msa_copy_s_h, 645 gen_helper_msa_copy_s_w, NULL_IF_MIPS32(gen_helper_msa_copy_s_d) 646 }; 647 648 return trans_msa_elm_fn(ctx, a, gen_msa_copy_s); 649 } 650 651 static bool trans_INSERT(DisasContext *ctx, arg_msa_elm_df *a) 652 { 653 static gen_helper_piii * const gen_msa_insert[4] = { 654 gen_helper_msa_insert_b, gen_helper_msa_insert_h, 655 gen_helper_msa_insert_w, NULL_IF_MIPS32(gen_helper_msa_insert_d) 656 }; 657 658 return trans_msa_elm_fn(ctx, a, gen_msa_insert); 659 } 660 661 static void gen_msa_elm(DisasContext *ctx) 662 { 663 uint8_t dfn = (ctx->opcode >> 16) & 0x3f; 664 665 if (dfn == 0x3E) { 666 /* CTCMSA, CFCMSA */ 667 gen_msa_elm_3e(ctx); 668 return; 669 } else { 670 gen_reserved_instruction(ctx); 671 return; 672 } 673 } 674 675 TRANS(FCAF, trans_msa_3rf, gen_helper_msa_fcaf_df); 676 TRANS(FCUN, trans_msa_3rf, gen_helper_msa_fcun_df); 677 TRANS(FCEQ, trans_msa_3rf, gen_helper_msa_fceq_df); 678 TRANS(FCUEQ, trans_msa_3rf, gen_helper_msa_fcueq_df); 679 TRANS(FCLT, trans_msa_3rf, gen_helper_msa_fclt_df); 680 TRANS(FCULT, trans_msa_3rf, gen_helper_msa_fcult_df); 681 TRANS(FCLE, trans_msa_3rf, gen_helper_msa_fcle_df); 682 TRANS(FCULE, trans_msa_3rf, gen_helper_msa_fcule_df); 683 TRANS(FSAF, trans_msa_3rf, gen_helper_msa_fsaf_df); 684 TRANS(FSUN, trans_msa_3rf, gen_helper_msa_fsun_df); 685 TRANS(FSEQ, trans_msa_3rf, gen_helper_msa_fseq_df); 686 TRANS(FSUEQ, trans_msa_3rf, gen_helper_msa_fsueq_df); 687 TRANS(FSLT, trans_msa_3rf, gen_helper_msa_fslt_df); 688 TRANS(FSULT, trans_msa_3rf, gen_helper_msa_fsult_df); 689 TRANS(FSLE, trans_msa_3rf, gen_helper_msa_fsle_df); 690 TRANS(FSULE, trans_msa_3rf, gen_helper_msa_fsule_df); 691 692 TRANS(FADD, trans_msa_3rf, gen_helper_msa_fadd_df); 693 TRANS(FSUB, trans_msa_3rf, gen_helper_msa_fsub_df); 694 TRANS(FMUL, trans_msa_3rf, gen_helper_msa_fmul_df); 695 TRANS(FDIV, trans_msa_3rf, gen_helper_msa_fdiv_df); 696 TRANS(FMADD, trans_msa_3rf, gen_helper_msa_fmadd_df); 697 TRANS(FMSUB, trans_msa_3rf, gen_helper_msa_fmsub_df); 698 TRANS(FEXP2, trans_msa_3rf, gen_helper_msa_fexp2_df); 699 TRANS(FEXDO, trans_msa_3rf, gen_helper_msa_fexdo_df); 700 TRANS(FTQ, trans_msa_3rf, gen_helper_msa_ftq_df); 701 TRANS(FMIN, trans_msa_3rf, gen_helper_msa_fmin_df); 702 TRANS(FMIN_A, trans_msa_3rf, gen_helper_msa_fmin_a_df); 703 TRANS(FMAX, trans_msa_3rf, gen_helper_msa_fmax_df); 704 TRANS(FMAX_A, trans_msa_3rf, gen_helper_msa_fmax_a_df); 705 706 TRANS(FCOR, trans_msa_3rf, gen_helper_msa_fcor_df); 707 TRANS(FCUNE, trans_msa_3rf, gen_helper_msa_fcune_df); 708 TRANS(FCNE, trans_msa_3rf, gen_helper_msa_fcne_df); 709 TRANS(MUL_Q, trans_msa_3rf, gen_helper_msa_mul_q_df); 710 TRANS(MADD_Q, trans_msa_3rf, gen_helper_msa_madd_q_df); 711 TRANS(MSUB_Q, trans_msa_3rf, gen_helper_msa_msub_q_df); 712 TRANS(FSOR, trans_msa_3rf, gen_helper_msa_fsor_df); 713 TRANS(FSUNE, trans_msa_3rf, gen_helper_msa_fsune_df); 714 TRANS(FSNE, trans_msa_3rf, gen_helper_msa_fsne_df); 715 TRANS(MULR_Q, trans_msa_3rf, gen_helper_msa_mulr_q_df); 716 TRANS(MADDR_Q, trans_msa_3rf, gen_helper_msa_maddr_q_df); 717 TRANS(MSUBR_Q, trans_msa_3rf, gen_helper_msa_msubr_q_df); 718 719 static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a, 720 gen_helper_pii *gen_msa_2r) 721 { 722 if (!check_msa_enabled(ctx)) { 723 return true; 724 } 725 726 gen_msa_2r(cpu_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws)); 727 728 return true; 729 } 730 731 TRANS_DF_ii(PCNT, trans_msa_2r, gen_helper_msa_pcnt); 732 TRANS_DF_ii(NLOC, trans_msa_2r, gen_helper_msa_nloc); 733 TRANS_DF_ii(NLZC, trans_msa_2r, gen_helper_msa_nlzc); 734 735 static bool trans_FILL(DisasContext *ctx, arg_msa_r *a) 736 { 737 if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) { 738 /* Double format valid only for MIPS64 */ 739 return false; 740 } 741 742 if (!check_msa_enabled(ctx)) { 743 return true; 744 } 745 746 gen_helper_msa_fill_df(cpu_env, 747 tcg_constant_i32(a->df), 748 tcg_constant_i32(a->wd), 749 tcg_constant_i32(a->ws)); 750 751 return true; 752 } 753 754 static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a, 755 gen_helper_piii *gen_msa_2rf) 756 { 757 if (!check_msa_enabled(ctx)) { 758 return true; 759 } 760 761 gen_msa_2rf(cpu_env, 762 tcg_constant_i32(a->df), 763 tcg_constant_i32(a->wd), 764 tcg_constant_i32(a->ws)); 765 766 return true; 767 } 768 769 TRANS(FCLASS, trans_msa_2rf, gen_helper_msa_fclass_df); 770 TRANS(FTRUNC_S, trans_msa_2rf, gen_helper_msa_fclass_df); 771 TRANS(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_s_df); 772 TRANS(FSQRT, trans_msa_2rf, gen_helper_msa_fsqrt_df); 773 TRANS(FRSQRT, trans_msa_2rf, gen_helper_msa_frsqrt_df); 774 TRANS(FRCP, trans_msa_2rf, gen_helper_msa_frcp_df); 775 TRANS(FRINT, trans_msa_2rf, gen_helper_msa_frint_df); 776 TRANS(FLOG2, trans_msa_2rf, gen_helper_msa_flog2_df); 777 TRANS(FEXUPL, trans_msa_2rf, gen_helper_msa_fexupl_df); 778 TRANS(FEXUPR, trans_msa_2rf, gen_helper_msa_fexupr_df); 779 TRANS(FFQL, trans_msa_2rf, gen_helper_msa_ffql_df); 780 TRANS(FFQR, trans_msa_2rf, gen_helper_msa_ffqr_df); 781 TRANS(FTINT_S, trans_msa_2rf, gen_helper_msa_ftint_s_df); 782 TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df); 783 TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); 784 TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); 785 786 static bool trans_MSA(DisasContext *ctx, arg_MSA *a) 787 { 788 uint32_t opcode = ctx->opcode; 789 790 if (!check_msa_enabled(ctx)) { 791 return true; 792 } 793 794 switch (MASK_MSA_MINOR(opcode)) { 795 case OPC_MSA_ELM: 796 gen_msa_elm(ctx); 797 break; 798 default: 799 MIPS_INVAL("MSA instruction"); 800 gen_reserved_instruction(ctx); 801 break; 802 } 803 804 return true; 805 } 806 807 static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, 808 gen_helper_piv *gen_msa_ldst) 809 { 810 TCGv taddr; 811 812 if (!check_msa_enabled(ctx)) { 813 return true; 814 } 815 816 taddr = tcg_temp_new(); 817 818 gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df); 819 gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr); 820 821 tcg_temp_free(taddr); 822 823 return true; 824 } 825 826 TRANS_DF_iv(LD, trans_msa_ldst, gen_helper_msa_ld); 827 TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st); 828 829 static bool trans_LSA(DisasContext *ctx, arg_r *a) 830 { 831 return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); 832 } 833 834 static bool trans_DLSA(DisasContext *ctx, arg_r *a) 835 { 836 if (TARGET_LONG_BITS != 64) { 837 return false; 838 } 839 return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); 840 } 841