1 /* 2 * MIPS SIMD Architecture (MSA) translation routines 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * Copyright (c) 2006 Marius Groeger (FPU operations) 6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) 7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) 8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) 9 * Copyright (c) 2020 Philippe Mathieu-Daudé 10 * 11 * SPDX-License-Identifier: LGPL-2.1-or-later 12 */ 13 #include "qemu/osdep.h" 14 #include "tcg/tcg-op.h" 15 #include "exec/helper-gen.h" 16 #include "translate.h" 17 #include "fpu_helper.h" 18 #include "internal.h" 19 20 static int elm_n(DisasContext *ctx, int x); 21 static int elm_df(DisasContext *ctx, int x); 22 static int bit_m(DisasContext *ctx, int x); 23 static int bit_df(DisasContext *ctx, int x); 24 25 static inline int plus_1(DisasContext *s, int x) 26 { 27 return x + 1; 28 } 29 30 static inline int plus_2(DisasContext *s, int x) 31 { 32 return x + 2; 33 } 34 35 /* Include the auto-generated decoder. */ 36 #include "decode-msa.c.inc" 37 38 #define OPC_MSA (0x1E << 26) 39 40 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 41 enum { 42 OPC_MSA_ELM = 0x19 | OPC_MSA, 43 }; 44 45 enum { 46 /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */ 47 OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, 48 OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, 49 OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, 50 }; 51 52 static const char msaregnames[][6] = { 53 "w0.d0", "w0.d1", "w1.d0", "w1.d1", 54 "w2.d0", "w2.d1", "w3.d0", "w3.d1", 55 "w4.d0", "w4.d1", "w5.d0", "w5.d1", 56 "w6.d0", "w6.d1", "w7.d0", "w7.d1", 57 "w8.d0", "w8.d1", "w9.d0", "w9.d1", 58 "w10.d0", "w10.d1", "w11.d0", "w11.d1", 59 "w12.d0", "w12.d1", "w13.d0", "w13.d1", 60 "w14.d0", "w14.d1", "w15.d0", "w15.d1", 61 "w16.d0", "w16.d1", "w17.d0", "w17.d1", 62 "w18.d0", "w18.d1", "w19.d0", "w19.d1", 63 "w20.d0", "w20.d1", "w21.d0", "w21.d1", 64 "w22.d0", "w22.d1", "w23.d0", "w23.d1", 65 "w24.d0", "w24.d1", "w25.d0", "w25.d1", 66 "w26.d0", "w26.d1", "w27.d0", "w27.d1", 67 "w28.d0", "w28.d1", "w29.d0", "w29.d1", 68 "w30.d0", "w30.d1", "w31.d0", "w31.d1", 69 }; 70 71 /* Encoding of Operation Field (must be indexed by CPUMIPSMSADataFormat) */ 72 struct dfe { 73 int start; 74 int length; 75 uint32_t mask; 76 }; 77 78 /* 79 * Extract immediate from df/{m,n} format (used by ELM & BIT instructions). 80 * Returns the immediate value, or -1 if the format does not match. 81 */ 82 static int df_extract_val(DisasContext *ctx, int x, const struct dfe *s) 83 { 84 for (unsigned i = 0; i < 4; i++) { 85 if (extract32(x, s->start, s->length) == s->mask) { 86 return extract32(x, 0, s->start); 87 } 88 } 89 return -1; 90 } 91 92 /* 93 * Extract DataField from df/{m,n} format (used by ELM & BIT instructions). 94 * Returns the DataField, or -1 if the format does not match. 95 */ 96 static int df_extract_df(DisasContext *ctx, int x, const struct dfe *s) 97 { 98 for (unsigned i = 0; i < 4; i++) { 99 if (extract32(x, s->start, s->length) == s->mask) { 100 return i; 101 } 102 } 103 return -1; 104 } 105 106 static const struct dfe df_elm[] = { 107 /* Table 3.26 ELM Instruction Format */ 108 [DF_BYTE] = {4, 2, 0b00}, 109 [DF_HALF] = {3, 3, 0b100}, 110 [DF_WORD] = {2, 4, 0b1100}, 111 [DF_DOUBLE] = {1, 5, 0b11100} 112 }; 113 114 static int elm_n(DisasContext *ctx, int x) 115 { 116 return df_extract_val(ctx, x, df_elm); 117 } 118 119 static int elm_df(DisasContext *ctx, int x) 120 { 121 return df_extract_df(ctx, x, df_elm); 122 } 123 124 static const struct dfe df_bit[] = { 125 /* Table 3.28 BIT Instruction Format */ 126 [DF_BYTE] = {3, 4, 0b1110}, 127 [DF_HALF] = {4, 3, 0b110}, 128 [DF_WORD] = {5, 2, 0b10}, 129 [DF_DOUBLE] = {6, 1, 0b0} 130 }; 131 132 static int bit_m(DisasContext *ctx, int x) 133 { 134 return df_extract_val(ctx, x, df_bit); 135 } 136 137 static int bit_df(DisasContext *ctx, int x) 138 { 139 return df_extract_df(ctx, x, df_bit); 140 } 141 142 static TCGv_i64 msa_wr_d[64]; 143 144 void msa_translate_init(void) 145 { 146 int i; 147 148 for (i = 0; i < 32; i++) { 149 int off; 150 151 /* 152 * The MSA vector registers are mapped on the 153 * scalar floating-point unit (FPU) registers. 154 */ 155 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); 156 msa_wr_d[i * 2] = fpu_f64[i]; 157 158 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); 159 msa_wr_d[i * 2 + 1] = 160 tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]); 161 } 162 } 163 164 /* 165 * Check if MSA is enabled. 166 * This function is always called with MSA available. 167 * If MSA is disabled, raise an exception. 168 */ 169 static inline bool check_msa_enabled(DisasContext *ctx) 170 { 171 if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && 172 !(ctx->hflags & MIPS_HFLAG_F64))) { 173 gen_reserved_instruction(ctx); 174 return false; 175 } 176 177 if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { 178 generate_exception_end(ctx, EXCP_MSADIS); 179 return false; 180 } 181 return true; 182 } 183 184 typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv); 185 typedef void gen_helper_pii(TCGv_ptr, TCGv_i32, TCGv_i32); 186 typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); 187 typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); 188 189 #define TRANS_DF_x(TYPE, NAME, trans_func, gen_func) \ 190 static gen_helper_p##TYPE * const NAME##_tab[4] = { \ 191 gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d \ 192 }; \ 193 TRANS(NAME, trans_func, NAME##_tab[a->df]) 194 195 #define TRANS_DF_iv(NAME, trans_func, gen_func) \ 196 TRANS_DF_x(iv, NAME, trans_func, gen_func) 197 198 #define TRANS_DF_ii(NAME, trans_func, gen_func) \ 199 TRANS_DF_x(ii, NAME, trans_func, gen_func) 200 201 #define TRANS_DF_iii(NAME, trans_func, gen_func) \ 202 TRANS_DF_x(iii, NAME, trans_func, gen_func) 203 204 #define TRANS_DF_iii_b(NAME, trans_func, gen_func) \ 205 static gen_helper_piii * const NAME##_tab[4] = { \ 206 NULL, gen_func##_h, gen_func##_w, gen_func##_d \ 207 }; \ 208 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 209 { \ 210 return trans_func(ctx, a, NAME##_tab[a->df]); \ 211 } 212 213 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, 214 TCGCond cond) 215 { 216 /* generates tcg ops to check if any element is 0 */ 217 /* Note this function only works with MSA_WRLEN = 128 */ 218 uint64_t eval_zero_or_big = dup_const(df, 1); 219 uint64_t eval_big = eval_zero_or_big << ((8 << df) - 1); 220 TCGv_i64 t0 = tcg_temp_new_i64(); 221 TCGv_i64 t1 = tcg_temp_new_i64(); 222 223 tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big); 224 tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]); 225 tcg_gen_andi_i64(t0, t0, eval_big); 226 tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big); 227 tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]); 228 tcg_gen_andi_i64(t1, t1, eval_big); 229 tcg_gen_or_i64(t0, t0, t1); 230 /* if all bits are zero then all elements are not zero */ 231 /* if some bit is non-zero then some element is zero */ 232 tcg_gen_setcondi_i64(cond, t0, t0, 0); 233 tcg_gen_trunc_i64_tl(tresult, t0); 234 tcg_temp_free_i64(t0); 235 tcg_temp_free_i64(t1); 236 } 237 238 static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond) 239 { 240 TCGv_i64 t0; 241 242 if (!check_msa_enabled(ctx)) { 243 return true; 244 } 245 246 if (ctx->hflags & MIPS_HFLAG_BMASK) { 247 gen_reserved_instruction(ctx); 248 return true; 249 } 250 t0 = tcg_temp_new_i64(); 251 tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); 252 tcg_gen_setcondi_i64(cond, t0, t0, 0); 253 tcg_gen_trunc_i64_tl(bcond, t0); 254 tcg_temp_free_i64(t0); 255 256 ctx->btarget = ctx->base.pc_next + (sa << 2) + 4; 257 258 ctx->hflags |= MIPS_HFLAG_BC; 259 ctx->hflags |= MIPS_HFLAG_BDS32; 260 261 return true; 262 } 263 264 static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a) 265 { 266 return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_EQ); 267 } 268 269 static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a) 270 { 271 return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_NE); 272 } 273 274 static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int sa, bool if_not) 275 { 276 if (!check_msa_enabled(ctx)) { 277 return true; 278 } 279 280 if (ctx->hflags & MIPS_HFLAG_BMASK) { 281 gen_reserved_instruction(ctx); 282 return true; 283 } 284 285 gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE); 286 287 ctx->btarget = ctx->base.pc_next + (sa << 2) + 4; 288 ctx->hflags |= MIPS_HFLAG_BC; 289 ctx->hflags |= MIPS_HFLAG_BDS32; 290 291 return true; 292 } 293 294 static bool trans_BZ(DisasContext *ctx, arg_msa_bz *a) 295 { 296 return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, false); 297 } 298 299 static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a) 300 { 301 return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true); 302 } 303 304 static bool trans_msa_i8(DisasContext *ctx, arg_msa_i *a, 305 gen_helper_piii *gen_msa_i8) 306 { 307 if (!check_msa_enabled(ctx)) { 308 return true; 309 } 310 311 gen_msa_i8(cpu_env, 312 tcg_constant_i32(a->wd), 313 tcg_constant_i32(a->ws), 314 tcg_constant_i32(a->sa)); 315 316 return true; 317 } 318 319 TRANS(ANDI, trans_msa_i8, gen_helper_msa_andi_b); 320 TRANS(ORI, trans_msa_i8, gen_helper_msa_ori_b); 321 TRANS(NORI, trans_msa_i8, gen_helper_msa_nori_b); 322 TRANS(XORI, trans_msa_i8, gen_helper_msa_xori_b); 323 TRANS(BMNZI, trans_msa_i8, gen_helper_msa_bmnzi_b); 324 TRANS(BMZI, trans_msa_i8, gen_helper_msa_bmzi_b); 325 TRANS(BSELI, trans_msa_i8, gen_helper_msa_bseli_b); 326 327 static bool trans_SHF(DisasContext *ctx, arg_msa_i *a) 328 { 329 if (a->df == DF_DOUBLE) { 330 return false; 331 } 332 333 if (!check_msa_enabled(ctx)) { 334 return true; 335 } 336 337 gen_helper_msa_shf_df(cpu_env, 338 tcg_constant_i32(a->df), 339 tcg_constant_i32(a->wd), 340 tcg_constant_i32(a->ws), 341 tcg_constant_i32(a->sa)); 342 343 return true; 344 } 345 346 static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *a, 347 gen_helper_piiii *gen_msa_i5) 348 { 349 if (!check_msa_enabled(ctx)) { 350 return true; 351 } 352 353 gen_msa_i5(cpu_env, 354 tcg_constant_i32(a->df), 355 tcg_constant_i32(a->wd), 356 tcg_constant_i32(a->ws), 357 tcg_constant_i32(a->sa)); 358 359 return true; 360 } 361 362 TRANS(ADDVI, trans_msa_i5, gen_helper_msa_addvi_df); 363 TRANS(SUBVI, trans_msa_i5, gen_helper_msa_subvi_df); 364 TRANS(MAXI_S, trans_msa_i5, gen_helper_msa_maxi_s_df); 365 TRANS(MAXI_U, trans_msa_i5, gen_helper_msa_maxi_u_df); 366 TRANS(MINI_S, trans_msa_i5, gen_helper_msa_mini_s_df); 367 TRANS(MINI_U, trans_msa_i5, gen_helper_msa_mini_u_df); 368 TRANS(CLTI_S, trans_msa_i5, gen_helper_msa_clti_s_df); 369 TRANS(CLTI_U, trans_msa_i5, gen_helper_msa_clti_u_df); 370 TRANS(CLEI_S, trans_msa_i5, gen_helper_msa_clei_s_df); 371 TRANS(CLEI_U, trans_msa_i5, gen_helper_msa_clei_u_df); 372 TRANS(CEQI, trans_msa_i5, gen_helper_msa_ceqi_df); 373 374 static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a) 375 { 376 if (!check_msa_enabled(ctx)) { 377 return true; 378 } 379 380 gen_helper_msa_ldi_df(cpu_env, 381 tcg_constant_i32(a->df), 382 tcg_constant_i32(a->wd), 383 tcg_constant_i32(a->sa)); 384 385 return true; 386 } 387 388 static bool trans_msa_bit(DisasContext *ctx, arg_msa_bit *a, 389 gen_helper_piiii *gen_msa_bit) 390 { 391 if (a->df < 0) { 392 return false; 393 } 394 395 if (!check_msa_enabled(ctx)) { 396 return true; 397 } 398 399 gen_msa_bit(cpu_env, 400 tcg_constant_i32(a->df), 401 tcg_constant_i32(a->wd), 402 tcg_constant_i32(a->ws), 403 tcg_constant_i32(a->m)); 404 405 return true; 406 } 407 408 TRANS(SLLI, trans_msa_bit, gen_helper_msa_slli_df); 409 TRANS(SRAI, trans_msa_bit, gen_helper_msa_srai_df); 410 TRANS(SRLI, trans_msa_bit, gen_helper_msa_srli_df); 411 TRANS(BCLRI, trans_msa_bit, gen_helper_msa_bclri_df); 412 TRANS(BSETI, trans_msa_bit, gen_helper_msa_bseti_df); 413 TRANS(BNEGI, trans_msa_bit, gen_helper_msa_bnegi_df); 414 TRANS(BINSLI, trans_msa_bit, gen_helper_msa_binsli_df); 415 TRANS(BINSRI, trans_msa_bit, gen_helper_msa_binsri_df); 416 TRANS(SAT_S, trans_msa_bit, gen_helper_msa_sat_u_df); 417 TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df); 418 TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df); 419 TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); 420 421 static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a, 422 gen_helper_piiii *gen_msa_3rf) 423 { 424 if (!check_msa_enabled(ctx)) { 425 return true; 426 } 427 428 gen_msa_3rf(cpu_env, 429 tcg_constant_i32(a->df), 430 tcg_constant_i32(a->wd), 431 tcg_constant_i32(a->ws), 432 tcg_constant_i32(a->wt)); 433 434 return true; 435 } 436 437 static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, 438 gen_helper_piii *gen_msa_3r) 439 { 440 if (!gen_msa_3r) { 441 return false; 442 } 443 444 if (!check_msa_enabled(ctx)) { 445 return true; 446 } 447 448 gen_msa_3r(cpu_env, 449 tcg_constant_i32(a->wd), 450 tcg_constant_i32(a->ws), 451 tcg_constant_i32(a->wt)); 452 453 return true; 454 } 455 456 TRANS(AND_V, trans_msa_3r, gen_helper_msa_and_v); 457 TRANS(OR_V, trans_msa_3r, gen_helper_msa_or_v); 458 TRANS(NOR_V, trans_msa_3r, gen_helper_msa_nor_v); 459 TRANS(XOR_V, trans_msa_3r, gen_helper_msa_xor_v); 460 TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v); 461 TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); 462 TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); 463 464 TRANS_DF_iii(SLL, trans_msa_3r, gen_helper_msa_sll); 465 TRANS_DF_iii(SRA, trans_msa_3r, gen_helper_msa_sra); 466 TRANS_DF_iii(SRL, trans_msa_3r, gen_helper_msa_srl); 467 TRANS_DF_iii(BCLR, trans_msa_3r, gen_helper_msa_bclr); 468 TRANS_DF_iii(BSET, trans_msa_3r, gen_helper_msa_bset); 469 TRANS_DF_iii(BNEG, trans_msa_3r, gen_helper_msa_bneg); 470 TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl); 471 TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr); 472 473 TRANS_DF_iii(ADDV, trans_msa_3r, gen_helper_msa_addv); 474 TRANS_DF_iii(SUBV, trans_msa_3r, gen_helper_msa_subv); 475 TRANS_DF_iii(MAX_S, trans_msa_3r, gen_helper_msa_max_s); 476 TRANS_DF_iii(MAX_U, trans_msa_3r, gen_helper_msa_max_u); 477 TRANS_DF_iii(MIN_S, trans_msa_3r, gen_helper_msa_min_s); 478 TRANS_DF_iii(MIN_U, trans_msa_3r, gen_helper_msa_min_u); 479 TRANS_DF_iii(MAX_A, trans_msa_3r, gen_helper_msa_max_a); 480 TRANS_DF_iii(MIN_A, trans_msa_3r, gen_helper_msa_min_a); 481 482 TRANS_DF_iii(CEQ, trans_msa_3r, gen_helper_msa_ceq); 483 TRANS_DF_iii(CLT_S, trans_msa_3r, gen_helper_msa_clt_s); 484 TRANS_DF_iii(CLT_U, trans_msa_3r, gen_helper_msa_clt_u); 485 TRANS_DF_iii(CLE_S, trans_msa_3r, gen_helper_msa_cle_s); 486 TRANS_DF_iii(CLE_U, trans_msa_3r, gen_helper_msa_cle_u); 487 488 TRANS_DF_iii(ADD_A, trans_msa_3r, gen_helper_msa_add_a); 489 TRANS_DF_iii(ADDS_A, trans_msa_3r, gen_helper_msa_adds_a); 490 TRANS_DF_iii(ADDS_S, trans_msa_3r, gen_helper_msa_adds_s); 491 TRANS_DF_iii(ADDS_U, trans_msa_3r, gen_helper_msa_adds_u); 492 TRANS_DF_iii(AVE_S, trans_msa_3r, gen_helper_msa_ave_s); 493 TRANS_DF_iii(AVE_U, trans_msa_3r, gen_helper_msa_ave_u); 494 TRANS_DF_iii(AVER_S, trans_msa_3r, gen_helper_msa_aver_s); 495 TRANS_DF_iii(AVER_U, trans_msa_3r, gen_helper_msa_aver_u); 496 497 TRANS_DF_iii(SUBS_S, trans_msa_3r, gen_helper_msa_subs_s); 498 TRANS_DF_iii(SUBS_U, trans_msa_3r, gen_helper_msa_subs_u); 499 TRANS_DF_iii(SUBSUS_U, trans_msa_3r, gen_helper_msa_subsus_u); 500 TRANS_DF_iii(SUBSUU_S, trans_msa_3r, gen_helper_msa_subsuu_s); 501 TRANS_DF_iii(ASUB_S, trans_msa_3r, gen_helper_msa_asub_s); 502 TRANS_DF_iii(ASUB_U, trans_msa_3r, gen_helper_msa_asub_u); 503 504 TRANS_DF_iii(MULV, trans_msa_3r, gen_helper_msa_mulv); 505 TRANS_DF_iii(MADDV, trans_msa_3r, gen_helper_msa_maddv); 506 TRANS_DF_iii(MSUBV, trans_msa_3r, gen_helper_msa_msubv); 507 TRANS_DF_iii(DIV_S, trans_msa_3r, gen_helper_msa_div_s); 508 TRANS_DF_iii(DIV_U, trans_msa_3r, gen_helper_msa_div_u); 509 TRANS_DF_iii(MOD_S, trans_msa_3r, gen_helper_msa_mod_s); 510 TRANS_DF_iii(MOD_U, trans_msa_3r, gen_helper_msa_mod_u); 511 512 TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s); 513 TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u); 514 TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s); 515 TRANS_DF_iii_b(DPADD_U, trans_msa_3r, gen_helper_msa_dpadd_u); 516 TRANS_DF_iii_b(DPSUB_S, trans_msa_3r, gen_helper_msa_dpsub_s); 517 TRANS_DF_iii_b(DPSUB_U, trans_msa_3r, gen_helper_msa_dpsub_u); 518 519 TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df); 520 TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df); 521 TRANS_DF_iii(PCKEV, trans_msa_3r, gen_helper_msa_pckev); 522 TRANS_DF_iii(PCKOD, trans_msa_3r, gen_helper_msa_pckod); 523 TRANS_DF_iii(ILVL, trans_msa_3r, gen_helper_msa_ilvl); 524 TRANS_DF_iii(ILVR, trans_msa_3r, gen_helper_msa_ilvr); 525 TRANS_DF_iii(ILVEV, trans_msa_3r, gen_helper_msa_ilvev); 526 TRANS_DF_iii(ILVOD, trans_msa_3r, gen_helper_msa_ilvod); 527 528 TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df); 529 TRANS_DF_iii(SRAR, trans_msa_3r, gen_helper_msa_srar); 530 TRANS_DF_iii(SRLR, trans_msa_3r, gen_helper_msa_srlr); 531 TRANS_DF_iii_b(HADD_S, trans_msa_3r, gen_helper_msa_hadd_s); 532 TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u); 533 TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s); 534 TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u); 535 536 static void gen_msa_elm_3e(DisasContext *ctx) 537 { 538 #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) 539 uint8_t source = (ctx->opcode >> 11) & 0x1f; 540 uint8_t dest = (ctx->opcode >> 6) & 0x1f; 541 TCGv telm = tcg_temp_new(); 542 TCGv_i32 tsr = tcg_const_i32(source); 543 TCGv_i32 tdt = tcg_const_i32(dest); 544 545 switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { 546 case OPC_CTCMSA: 547 gen_load_gpr(telm, source); 548 gen_helper_msa_ctcmsa(cpu_env, telm, tdt); 549 break; 550 case OPC_CFCMSA: 551 gen_helper_msa_cfcmsa(telm, cpu_env, tsr); 552 gen_store_gpr(telm, dest); 553 break; 554 case OPC_MOVE_V: 555 gen_helper_msa_move_v(cpu_env, tdt, tsr); 556 break; 557 default: 558 MIPS_INVAL("MSA instruction"); 559 gen_reserved_instruction(ctx); 560 break; 561 } 562 563 tcg_temp_free(telm); 564 tcg_temp_free_i32(tdt); 565 tcg_temp_free_i32(tsr); 566 } 567 568 static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a, 569 gen_helper_piiii *gen_msa_elm_df) 570 { 571 if (a->df < 0) { 572 return false; 573 } 574 575 if (!check_msa_enabled(ctx)) { 576 return true; 577 } 578 579 gen_msa_elm_df(cpu_env, 580 tcg_constant_i32(a->df), 581 tcg_constant_i32(a->wd), 582 tcg_constant_i32(a->ws), 583 tcg_constant_i32(a->n)); 584 585 return true; 586 } 587 588 TRANS(SLDI, trans_msa_elm, gen_helper_msa_sldi_df); 589 TRANS(SPLATI, trans_msa_elm, gen_helper_msa_splati_df); 590 TRANS(INSVE, trans_msa_elm, gen_helper_msa_insve_df); 591 592 static bool trans_msa_elm_fn(DisasContext *ctx, arg_msa_elm_df *a, 593 gen_helper_piii * const gen_msa_elm[4]) 594 { 595 if (a->df < 0 || !gen_msa_elm[a->df]) { 596 return false; 597 } 598 599 if (check_msa_enabled(ctx)) { 600 return true; 601 } 602 603 if (a->wd == 0) { 604 /* Treat as NOP. */ 605 return true; 606 } 607 608 gen_msa_elm[a->df](cpu_env, 609 tcg_constant_i32(a->wd), 610 tcg_constant_i32(a->ws), 611 tcg_constant_i32(a->n)); 612 613 return true; 614 } 615 616 #if defined(TARGET_MIPS64) 617 #define NULL_IF_MIPS32(function) function 618 #else 619 #define NULL_IF_MIPS32(function) NULL 620 #endif 621 622 static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a) 623 { 624 static gen_helper_piii * const gen_msa_copy_u[4] = { 625 gen_helper_msa_copy_u_b, gen_helper_msa_copy_u_h, 626 NULL_IF_MIPS32(gen_helper_msa_copy_u_w), NULL 627 }; 628 629 return trans_msa_elm_fn(ctx, a, gen_msa_copy_u); 630 } 631 632 static bool trans_COPY_S(DisasContext *ctx, arg_msa_elm_df *a) 633 { 634 static gen_helper_piii * const gen_msa_copy_s[4] = { 635 gen_helper_msa_copy_s_b, gen_helper_msa_copy_s_h, 636 gen_helper_msa_copy_s_w, NULL_IF_MIPS32(gen_helper_msa_copy_s_d) 637 }; 638 639 return trans_msa_elm_fn(ctx, a, gen_msa_copy_s); 640 } 641 642 static bool trans_INSERT(DisasContext *ctx, arg_msa_elm_df *a) 643 { 644 static gen_helper_piii * const gen_msa_insert[4] = { 645 gen_helper_msa_insert_b, gen_helper_msa_insert_h, 646 gen_helper_msa_insert_w, NULL_IF_MIPS32(gen_helper_msa_insert_d) 647 }; 648 649 return trans_msa_elm_fn(ctx, a, gen_msa_insert); 650 } 651 652 static void gen_msa_elm(DisasContext *ctx) 653 { 654 uint8_t dfn = (ctx->opcode >> 16) & 0x3f; 655 656 if (dfn == 0x3E) { 657 /* CTCMSA, CFCMSA, MOVE.V */ 658 gen_msa_elm_3e(ctx); 659 return; 660 } else { 661 gen_reserved_instruction(ctx); 662 return; 663 } 664 } 665 666 TRANS(FCAF, trans_msa_3rf, gen_helper_msa_fcaf_df); 667 TRANS(FCUN, trans_msa_3rf, gen_helper_msa_fcun_df); 668 TRANS(FCEQ, trans_msa_3rf, gen_helper_msa_fceq_df); 669 TRANS(FCUEQ, trans_msa_3rf, gen_helper_msa_fcueq_df); 670 TRANS(FCLT, trans_msa_3rf, gen_helper_msa_fclt_df); 671 TRANS(FCULT, trans_msa_3rf, gen_helper_msa_fcult_df); 672 TRANS(FCLE, trans_msa_3rf, gen_helper_msa_fcle_df); 673 TRANS(FCULE, trans_msa_3rf, gen_helper_msa_fcule_df); 674 TRANS(FSAF, trans_msa_3rf, gen_helper_msa_fsaf_df); 675 TRANS(FSUN, trans_msa_3rf, gen_helper_msa_fsun_df); 676 TRANS(FSEQ, trans_msa_3rf, gen_helper_msa_fseq_df); 677 TRANS(FSUEQ, trans_msa_3rf, gen_helper_msa_fsueq_df); 678 TRANS(FSLT, trans_msa_3rf, gen_helper_msa_fslt_df); 679 TRANS(FSULT, trans_msa_3rf, gen_helper_msa_fsult_df); 680 TRANS(FSLE, trans_msa_3rf, gen_helper_msa_fsle_df); 681 TRANS(FSULE, trans_msa_3rf, gen_helper_msa_fsule_df); 682 683 TRANS(FADD, trans_msa_3rf, gen_helper_msa_fadd_df); 684 TRANS(FSUB, trans_msa_3rf, gen_helper_msa_fsub_df); 685 TRANS(FMUL, trans_msa_3rf, gen_helper_msa_fmul_df); 686 TRANS(FDIV, trans_msa_3rf, gen_helper_msa_fdiv_df); 687 TRANS(FMADD, trans_msa_3rf, gen_helper_msa_fmadd_df); 688 TRANS(FMSUB, trans_msa_3rf, gen_helper_msa_fmsub_df); 689 TRANS(FEXP2, trans_msa_3rf, gen_helper_msa_fexp2_df); 690 TRANS(FEXDO, trans_msa_3rf, gen_helper_msa_fexdo_df); 691 TRANS(FTQ, trans_msa_3rf, gen_helper_msa_ftq_df); 692 TRANS(FMIN, trans_msa_3rf, gen_helper_msa_fmin_df); 693 TRANS(FMIN_A, trans_msa_3rf, gen_helper_msa_fmin_a_df); 694 TRANS(FMAX, trans_msa_3rf, gen_helper_msa_fmax_df); 695 TRANS(FMAX_A, trans_msa_3rf, gen_helper_msa_fmax_a_df); 696 697 TRANS(FCOR, trans_msa_3rf, gen_helper_msa_fcor_df); 698 TRANS(FCUNE, trans_msa_3rf, gen_helper_msa_fcune_df); 699 TRANS(FCNE, trans_msa_3rf, gen_helper_msa_fcne_df); 700 TRANS(MUL_Q, trans_msa_3rf, gen_helper_msa_mul_q_df); 701 TRANS(MADD_Q, trans_msa_3rf, gen_helper_msa_madd_q_df); 702 TRANS(MSUB_Q, trans_msa_3rf, gen_helper_msa_msub_q_df); 703 TRANS(FSOR, trans_msa_3rf, gen_helper_msa_fsor_df); 704 TRANS(FSUNE, trans_msa_3rf, gen_helper_msa_fsune_df); 705 TRANS(FSNE, trans_msa_3rf, gen_helper_msa_fsne_df); 706 TRANS(MULR_Q, trans_msa_3rf, gen_helper_msa_mulr_q_df); 707 TRANS(MADDR_Q, trans_msa_3rf, gen_helper_msa_maddr_q_df); 708 TRANS(MSUBR_Q, trans_msa_3rf, gen_helper_msa_msubr_q_df); 709 710 static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a, 711 gen_helper_pii *gen_msa_2r) 712 { 713 if (!check_msa_enabled(ctx)) { 714 return true; 715 } 716 717 gen_msa_2r(cpu_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws)); 718 719 return true; 720 } 721 722 TRANS_DF_ii(PCNT, trans_msa_2r, gen_helper_msa_pcnt); 723 TRANS_DF_ii(NLOC, trans_msa_2r, gen_helper_msa_nloc); 724 TRANS_DF_ii(NLZC, trans_msa_2r, gen_helper_msa_nlzc); 725 726 static bool trans_FILL(DisasContext *ctx, arg_msa_r *a) 727 { 728 if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) { 729 /* Double format valid only for MIPS64 */ 730 return false; 731 } 732 733 if (!check_msa_enabled(ctx)) { 734 return true; 735 } 736 737 gen_helper_msa_fill_df(cpu_env, 738 tcg_constant_i32(a->df), 739 tcg_constant_i32(a->wd), 740 tcg_constant_i32(a->ws)); 741 742 return true; 743 } 744 745 static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a, 746 gen_helper_piii *gen_msa_2rf) 747 { 748 if (!check_msa_enabled(ctx)) { 749 return true; 750 } 751 752 gen_msa_2rf(cpu_env, 753 tcg_constant_i32(a->df), 754 tcg_constant_i32(a->wd), 755 tcg_constant_i32(a->ws)); 756 757 return true; 758 } 759 760 TRANS(FCLASS, trans_msa_2rf, gen_helper_msa_fclass_df); 761 TRANS(FTRUNC_S, trans_msa_2rf, gen_helper_msa_fclass_df); 762 TRANS(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_s_df); 763 TRANS(FSQRT, trans_msa_2rf, gen_helper_msa_fsqrt_df); 764 TRANS(FRSQRT, trans_msa_2rf, gen_helper_msa_frsqrt_df); 765 TRANS(FRCP, trans_msa_2rf, gen_helper_msa_frcp_df); 766 TRANS(FRINT, trans_msa_2rf, gen_helper_msa_frint_df); 767 TRANS(FLOG2, trans_msa_2rf, gen_helper_msa_flog2_df); 768 TRANS(FEXUPL, trans_msa_2rf, gen_helper_msa_fexupl_df); 769 TRANS(FEXUPR, trans_msa_2rf, gen_helper_msa_fexupr_df); 770 TRANS(FFQL, trans_msa_2rf, gen_helper_msa_ffql_df); 771 TRANS(FFQR, trans_msa_2rf, gen_helper_msa_ffqr_df); 772 TRANS(FTINT_S, trans_msa_2rf, gen_helper_msa_ftint_s_df); 773 TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df); 774 TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); 775 TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); 776 777 static bool trans_MSA(DisasContext *ctx, arg_MSA *a) 778 { 779 uint32_t opcode = ctx->opcode; 780 781 if (!check_msa_enabled(ctx)) { 782 return true; 783 } 784 785 switch (MASK_MSA_MINOR(opcode)) { 786 case OPC_MSA_ELM: 787 gen_msa_elm(ctx); 788 break; 789 default: 790 MIPS_INVAL("MSA instruction"); 791 gen_reserved_instruction(ctx); 792 break; 793 } 794 795 return true; 796 } 797 798 static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, 799 gen_helper_piv *gen_msa_ldst) 800 { 801 TCGv taddr; 802 803 if (!check_msa_enabled(ctx)) { 804 return true; 805 } 806 807 taddr = tcg_temp_new(); 808 809 gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df); 810 gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr); 811 812 tcg_temp_free(taddr); 813 814 return true; 815 } 816 817 TRANS_DF_iv(LD, trans_msa_ldst, gen_helper_msa_ld); 818 TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st); 819 820 static bool trans_LSA(DisasContext *ctx, arg_r *a) 821 { 822 return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); 823 } 824 825 static bool trans_DLSA(DisasContext *ctx, arg_r *a) 826 { 827 if (TARGET_LONG_BITS != 64) { 828 return false; 829 } 830 return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); 831 } 832