1 /* 2 * MIPS SIMD Architecture (MSA) translation routines 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * Copyright (c) 2006 Marius Groeger (FPU operations) 6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) 7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) 8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) 9 * Copyright (c) 2020 Philippe Mathieu-Daudé 10 * 11 * SPDX-License-Identifier: LGPL-2.1-or-later 12 */ 13 #include "qemu/osdep.h" 14 #include "tcg/tcg-op.h" 15 #include "exec/helper-gen.h" 16 #include "translate.h" 17 #include "fpu_helper.h" 18 #include "internal.h" 19 20 static int elm_n(DisasContext *ctx, int x); 21 static int elm_df(DisasContext *ctx, int x); 22 static int bit_m(DisasContext *ctx, int x); 23 static int bit_df(DisasContext *ctx, int x); 24 25 static inline int plus_1(DisasContext *s, int x) 26 { 27 return x + 1; 28 } 29 30 static inline int plus_2(DisasContext *s, int x) 31 { 32 return x + 2; 33 } 34 35 /* Include the auto-generated decoder. */ 36 #include "decode-msa.c.inc" 37 38 #define OPC_MSA (0x1E << 26) 39 40 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) 41 enum { 42 OPC_MSA_ELM = 0x19 | OPC_MSA, 43 }; 44 45 enum { 46 /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */ 47 OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, 48 OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, 49 OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM, 50 OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, 51 OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, 52 }; 53 54 static const char msaregnames[][6] = { 55 "w0.d0", "w0.d1", "w1.d0", "w1.d1", 56 "w2.d0", "w2.d1", "w3.d0", "w3.d1", 57 "w4.d0", "w4.d1", "w5.d0", "w5.d1", 58 "w6.d0", "w6.d1", "w7.d0", "w7.d1", 59 "w8.d0", "w8.d1", "w9.d0", "w9.d1", 60 "w10.d0", "w10.d1", "w11.d0", "w11.d1", 61 "w12.d0", "w12.d1", "w13.d0", "w13.d1", 62 "w14.d0", "w14.d1", "w15.d0", "w15.d1", 63 "w16.d0", "w16.d1", "w17.d0", "w17.d1", 64 "w18.d0", "w18.d1", "w19.d0", "w19.d1", 65 "w20.d0", "w20.d1", "w21.d0", "w21.d1", 66 "w22.d0", "w22.d1", "w23.d0", "w23.d1", 67 "w24.d0", "w24.d1", "w25.d0", "w25.d1", 68 "w26.d0", "w26.d1", "w27.d0", "w27.d1", 69 "w28.d0", "w28.d1", "w29.d0", "w29.d1", 70 "w30.d0", "w30.d1", "w31.d0", "w31.d1", 71 }; 72 73 /* Encoding of Operation Field (must be indexed by CPUMIPSMSADataFormat) */ 74 struct dfe { 75 int start; 76 int length; 77 uint32_t mask; 78 }; 79 80 /* 81 * Extract immediate from df/{m,n} format (used by ELM & BIT instructions). 82 * Returns the immediate value, or -1 if the format does not match. 83 */ 84 static int df_extract_val(DisasContext *ctx, int x, const struct dfe *s) 85 { 86 for (unsigned i = 0; i < 4; i++) { 87 if (extract32(x, s->start, s->length) == s->mask) { 88 return extract32(x, 0, s->start); 89 } 90 } 91 return -1; 92 } 93 94 /* 95 * Extract DataField from df/{m,n} format (used by ELM & BIT instructions). 96 * Returns the DataField, or -1 if the format does not match. 97 */ 98 static int df_extract_df(DisasContext *ctx, int x, const struct dfe *s) 99 { 100 for (unsigned i = 0; i < 4; i++) { 101 if (extract32(x, s->start, s->length) == s->mask) { 102 return i; 103 } 104 } 105 return -1; 106 } 107 108 static const struct dfe df_elm[] = { 109 /* Table 3.26 ELM Instruction Format */ 110 [DF_BYTE] = {4, 2, 0b00}, 111 [DF_HALF] = {3, 3, 0b100}, 112 [DF_WORD] = {2, 4, 0b1100}, 113 [DF_DOUBLE] = {1, 5, 0b11100} 114 }; 115 116 static int elm_n(DisasContext *ctx, int x) 117 { 118 return df_extract_val(ctx, x, df_elm); 119 } 120 121 static int elm_df(DisasContext *ctx, int x) 122 { 123 return df_extract_df(ctx, x, df_elm); 124 } 125 126 static const struct dfe df_bit[] = { 127 /* Table 3.28 BIT Instruction Format */ 128 [DF_BYTE] = {3, 4, 0b1110}, 129 [DF_HALF] = {4, 3, 0b110}, 130 [DF_WORD] = {5, 2, 0b10}, 131 [DF_DOUBLE] = {6, 1, 0b0} 132 }; 133 134 static int bit_m(DisasContext *ctx, int x) 135 { 136 return df_extract_val(ctx, x, df_bit); 137 } 138 139 static int bit_df(DisasContext *ctx, int x) 140 { 141 return df_extract_df(ctx, x, df_bit); 142 } 143 144 static TCGv_i64 msa_wr_d[64]; 145 146 void msa_translate_init(void) 147 { 148 int i; 149 150 for (i = 0; i < 32; i++) { 151 int off; 152 153 /* 154 * The MSA vector registers are mapped on the 155 * scalar floating-point unit (FPU) registers. 156 */ 157 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); 158 msa_wr_d[i * 2] = fpu_f64[i]; 159 160 off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); 161 msa_wr_d[i * 2 + 1] = 162 tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]); 163 } 164 } 165 166 /* 167 * Check if MSA is enabled. 168 * This function is always called with MSA available. 169 * If MSA is disabled, raise an exception. 170 */ 171 static inline bool check_msa_enabled(DisasContext *ctx) 172 { 173 if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && 174 !(ctx->hflags & MIPS_HFLAG_F64))) { 175 gen_reserved_instruction(ctx); 176 return false; 177 } 178 179 if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { 180 generate_exception_end(ctx, EXCP_MSADIS); 181 return false; 182 } 183 return true; 184 } 185 186 typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv); 187 typedef void gen_helper_pii(TCGv_ptr, TCGv_i32, TCGv_i32); 188 typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); 189 typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); 190 191 #define TRANS_DF_x(TYPE, NAME, trans_func, gen_func) \ 192 static gen_helper_p##TYPE * const NAME##_tab[4] = { \ 193 gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d \ 194 }; \ 195 TRANS(NAME, trans_func, NAME##_tab[a->df]) 196 197 #define TRANS_DF_iv(NAME, trans_func, gen_func) \ 198 TRANS_DF_x(iv, NAME, trans_func, gen_func) 199 200 #define TRANS_DF_ii(NAME, trans_func, gen_func) \ 201 TRANS_DF_x(ii, NAME, trans_func, gen_func) 202 203 #define TRANS_DF_iii(NAME, trans_func, gen_func) \ 204 TRANS_DF_x(iii, NAME, trans_func, gen_func) 205 206 #define TRANS_DF_iii_b(NAME, trans_func, gen_func) \ 207 static gen_helper_piii * const NAME##_tab[4] = { \ 208 NULL, gen_func##_h, gen_func##_w, gen_func##_d \ 209 }; \ 210 static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ 211 { \ 212 return trans_func(ctx, a, NAME##_tab[a->df]); \ 213 } 214 215 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, 216 TCGCond cond) 217 { 218 /* generates tcg ops to check if any element is 0 */ 219 /* Note this function only works with MSA_WRLEN = 128 */ 220 uint64_t eval_zero_or_big = dup_const(df, 1); 221 uint64_t eval_big = eval_zero_or_big << ((8 << df) - 1); 222 TCGv_i64 t0 = tcg_temp_new_i64(); 223 TCGv_i64 t1 = tcg_temp_new_i64(); 224 225 tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big); 226 tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]); 227 tcg_gen_andi_i64(t0, t0, eval_big); 228 tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big); 229 tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]); 230 tcg_gen_andi_i64(t1, t1, eval_big); 231 tcg_gen_or_i64(t0, t0, t1); 232 /* if all bits are zero then all elements are not zero */ 233 /* if some bit is non-zero then some element is zero */ 234 tcg_gen_setcondi_i64(cond, t0, t0, 0); 235 tcg_gen_trunc_i64_tl(tresult, t0); 236 tcg_temp_free_i64(t0); 237 tcg_temp_free_i64(t1); 238 } 239 240 static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond) 241 { 242 TCGv_i64 t0; 243 244 if (!check_msa_enabled(ctx)) { 245 return true; 246 } 247 248 if (ctx->hflags & MIPS_HFLAG_BMASK) { 249 gen_reserved_instruction(ctx); 250 return true; 251 } 252 t0 = tcg_temp_new_i64(); 253 tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); 254 tcg_gen_setcondi_i64(cond, t0, t0, 0); 255 tcg_gen_trunc_i64_tl(bcond, t0); 256 tcg_temp_free_i64(t0); 257 258 ctx->btarget = ctx->base.pc_next + (sa << 2) + 4; 259 260 ctx->hflags |= MIPS_HFLAG_BC; 261 ctx->hflags |= MIPS_HFLAG_BDS32; 262 263 return true; 264 } 265 266 static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a) 267 { 268 return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_EQ); 269 } 270 271 static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a) 272 { 273 return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_NE); 274 } 275 276 static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int sa, bool if_not) 277 { 278 if (!check_msa_enabled(ctx)) { 279 return true; 280 } 281 282 if (ctx->hflags & MIPS_HFLAG_BMASK) { 283 gen_reserved_instruction(ctx); 284 return true; 285 } 286 287 gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE); 288 289 ctx->btarget = ctx->base.pc_next + (sa << 2) + 4; 290 ctx->hflags |= MIPS_HFLAG_BC; 291 ctx->hflags |= MIPS_HFLAG_BDS32; 292 293 return true; 294 } 295 296 static bool trans_BZ(DisasContext *ctx, arg_msa_bz *a) 297 { 298 return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, false); 299 } 300 301 static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a) 302 { 303 return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true); 304 } 305 306 static bool trans_msa_i8(DisasContext *ctx, arg_msa_i *a, 307 gen_helper_piii *gen_msa_i8) 308 { 309 if (!check_msa_enabled(ctx)) { 310 return true; 311 } 312 313 gen_msa_i8(cpu_env, 314 tcg_constant_i32(a->wd), 315 tcg_constant_i32(a->ws), 316 tcg_constant_i32(a->sa)); 317 318 return true; 319 } 320 321 TRANS(ANDI, trans_msa_i8, gen_helper_msa_andi_b); 322 TRANS(ORI, trans_msa_i8, gen_helper_msa_ori_b); 323 TRANS(NORI, trans_msa_i8, gen_helper_msa_nori_b); 324 TRANS(XORI, trans_msa_i8, gen_helper_msa_xori_b); 325 TRANS(BMNZI, trans_msa_i8, gen_helper_msa_bmnzi_b); 326 TRANS(BMZI, trans_msa_i8, gen_helper_msa_bmzi_b); 327 TRANS(BSELI, trans_msa_i8, gen_helper_msa_bseli_b); 328 329 static bool trans_SHF(DisasContext *ctx, arg_msa_i *a) 330 { 331 if (a->df == DF_DOUBLE) { 332 return false; 333 } 334 335 if (!check_msa_enabled(ctx)) { 336 return true; 337 } 338 339 gen_helper_msa_shf_df(cpu_env, 340 tcg_constant_i32(a->df), 341 tcg_constant_i32(a->wd), 342 tcg_constant_i32(a->ws), 343 tcg_constant_i32(a->sa)); 344 345 return true; 346 } 347 348 static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *a, 349 gen_helper_piiii *gen_msa_i5) 350 { 351 if (!check_msa_enabled(ctx)) { 352 return true; 353 } 354 355 gen_msa_i5(cpu_env, 356 tcg_constant_i32(a->df), 357 tcg_constant_i32(a->wd), 358 tcg_constant_i32(a->ws), 359 tcg_constant_i32(a->sa)); 360 361 return true; 362 } 363 364 TRANS(ADDVI, trans_msa_i5, gen_helper_msa_addvi_df); 365 TRANS(SUBVI, trans_msa_i5, gen_helper_msa_subvi_df); 366 TRANS(MAXI_S, trans_msa_i5, gen_helper_msa_maxi_s_df); 367 TRANS(MAXI_U, trans_msa_i5, gen_helper_msa_maxi_u_df); 368 TRANS(MINI_S, trans_msa_i5, gen_helper_msa_mini_s_df); 369 TRANS(MINI_U, trans_msa_i5, gen_helper_msa_mini_u_df); 370 TRANS(CLTI_S, trans_msa_i5, gen_helper_msa_clti_s_df); 371 TRANS(CLTI_U, trans_msa_i5, gen_helper_msa_clti_u_df); 372 TRANS(CLEI_S, trans_msa_i5, gen_helper_msa_clei_s_df); 373 TRANS(CLEI_U, trans_msa_i5, gen_helper_msa_clei_u_df); 374 TRANS(CEQI, trans_msa_i5, gen_helper_msa_ceqi_df); 375 376 static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a) 377 { 378 if (!check_msa_enabled(ctx)) { 379 return true; 380 } 381 382 gen_helper_msa_ldi_df(cpu_env, 383 tcg_constant_i32(a->df), 384 tcg_constant_i32(a->wd), 385 tcg_constant_i32(a->sa)); 386 387 return true; 388 } 389 390 static bool trans_msa_bit(DisasContext *ctx, arg_msa_bit *a, 391 gen_helper_piiii *gen_msa_bit) 392 { 393 if (a->df < 0) { 394 return false; 395 } 396 397 if (!check_msa_enabled(ctx)) { 398 return true; 399 } 400 401 gen_msa_bit(cpu_env, 402 tcg_constant_i32(a->df), 403 tcg_constant_i32(a->wd), 404 tcg_constant_i32(a->ws), 405 tcg_constant_i32(a->m)); 406 407 return true; 408 } 409 410 TRANS(SLLI, trans_msa_bit, gen_helper_msa_slli_df); 411 TRANS(SRAI, trans_msa_bit, gen_helper_msa_srai_df); 412 TRANS(SRLI, trans_msa_bit, gen_helper_msa_srli_df); 413 TRANS(BCLRI, trans_msa_bit, gen_helper_msa_bclri_df); 414 TRANS(BSETI, trans_msa_bit, gen_helper_msa_bseti_df); 415 TRANS(BNEGI, trans_msa_bit, gen_helper_msa_bnegi_df); 416 TRANS(BINSLI, trans_msa_bit, gen_helper_msa_binsli_df); 417 TRANS(BINSRI, trans_msa_bit, gen_helper_msa_binsri_df); 418 TRANS(SAT_S, trans_msa_bit, gen_helper_msa_sat_u_df); 419 TRANS(SAT_U, trans_msa_bit, gen_helper_msa_sat_u_df); 420 TRANS(SRARI, trans_msa_bit, gen_helper_msa_srari_df); 421 TRANS(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df); 422 423 static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a, 424 gen_helper_piiii *gen_msa_3rf) 425 { 426 if (!check_msa_enabled(ctx)) { 427 return true; 428 } 429 430 gen_msa_3rf(cpu_env, 431 tcg_constant_i32(a->df), 432 tcg_constant_i32(a->wd), 433 tcg_constant_i32(a->ws), 434 tcg_constant_i32(a->wt)); 435 436 return true; 437 } 438 439 static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a, 440 gen_helper_piii *gen_msa_3r) 441 { 442 if (!gen_msa_3r) { 443 return false; 444 } 445 446 if (!check_msa_enabled(ctx)) { 447 return true; 448 } 449 450 gen_msa_3r(cpu_env, 451 tcg_constant_i32(a->wd), 452 tcg_constant_i32(a->ws), 453 tcg_constant_i32(a->wt)); 454 455 return true; 456 } 457 458 TRANS(AND_V, trans_msa_3r, gen_helper_msa_and_v); 459 TRANS(OR_V, trans_msa_3r, gen_helper_msa_or_v); 460 TRANS(NOR_V, trans_msa_3r, gen_helper_msa_nor_v); 461 TRANS(XOR_V, trans_msa_3r, gen_helper_msa_xor_v); 462 TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v); 463 TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); 464 TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); 465 466 TRANS_DF_iii(SLL, trans_msa_3r, gen_helper_msa_sll); 467 TRANS_DF_iii(SRA, trans_msa_3r, gen_helper_msa_sra); 468 TRANS_DF_iii(SRL, trans_msa_3r, gen_helper_msa_srl); 469 TRANS_DF_iii(BCLR, trans_msa_3r, gen_helper_msa_bclr); 470 TRANS_DF_iii(BSET, trans_msa_3r, gen_helper_msa_bset); 471 TRANS_DF_iii(BNEG, trans_msa_3r, gen_helper_msa_bneg); 472 TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl); 473 TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr); 474 475 TRANS_DF_iii(ADDV, trans_msa_3r, gen_helper_msa_addv); 476 TRANS_DF_iii(SUBV, trans_msa_3r, gen_helper_msa_subv); 477 TRANS_DF_iii(MAX_S, trans_msa_3r, gen_helper_msa_max_s); 478 TRANS_DF_iii(MAX_U, trans_msa_3r, gen_helper_msa_max_u); 479 TRANS_DF_iii(MIN_S, trans_msa_3r, gen_helper_msa_min_s); 480 TRANS_DF_iii(MIN_U, trans_msa_3r, gen_helper_msa_min_u); 481 TRANS_DF_iii(MAX_A, trans_msa_3r, gen_helper_msa_max_a); 482 TRANS_DF_iii(MIN_A, trans_msa_3r, gen_helper_msa_min_a); 483 484 TRANS_DF_iii(CEQ, trans_msa_3r, gen_helper_msa_ceq); 485 TRANS_DF_iii(CLT_S, trans_msa_3r, gen_helper_msa_clt_s); 486 TRANS_DF_iii(CLT_U, trans_msa_3r, gen_helper_msa_clt_u); 487 TRANS_DF_iii(CLE_S, trans_msa_3r, gen_helper_msa_cle_s); 488 TRANS_DF_iii(CLE_U, trans_msa_3r, gen_helper_msa_cle_u); 489 490 TRANS_DF_iii(ADD_A, trans_msa_3r, gen_helper_msa_add_a); 491 TRANS_DF_iii(ADDS_A, trans_msa_3r, gen_helper_msa_adds_a); 492 TRANS_DF_iii(ADDS_S, trans_msa_3r, gen_helper_msa_adds_s); 493 TRANS_DF_iii(ADDS_U, trans_msa_3r, gen_helper_msa_adds_u); 494 TRANS_DF_iii(AVE_S, trans_msa_3r, gen_helper_msa_ave_s); 495 TRANS_DF_iii(AVE_U, trans_msa_3r, gen_helper_msa_ave_u); 496 TRANS_DF_iii(AVER_S, trans_msa_3r, gen_helper_msa_aver_s); 497 TRANS_DF_iii(AVER_U, trans_msa_3r, gen_helper_msa_aver_u); 498 499 TRANS_DF_iii(SUBS_S, trans_msa_3r, gen_helper_msa_subs_s); 500 TRANS_DF_iii(SUBS_U, trans_msa_3r, gen_helper_msa_subs_u); 501 TRANS_DF_iii(SUBSUS_U, trans_msa_3r, gen_helper_msa_subsus_u); 502 TRANS_DF_iii(SUBSUU_S, trans_msa_3r, gen_helper_msa_subsuu_s); 503 TRANS_DF_iii(ASUB_S, trans_msa_3r, gen_helper_msa_asub_s); 504 TRANS_DF_iii(ASUB_U, trans_msa_3r, gen_helper_msa_asub_u); 505 506 TRANS_DF_iii(MULV, trans_msa_3r, gen_helper_msa_mulv); 507 TRANS_DF_iii(MADDV, trans_msa_3r, gen_helper_msa_maddv); 508 TRANS_DF_iii(MSUBV, trans_msa_3r, gen_helper_msa_msubv); 509 TRANS_DF_iii(DIV_S, trans_msa_3r, gen_helper_msa_div_s); 510 TRANS_DF_iii(DIV_U, trans_msa_3r, gen_helper_msa_div_u); 511 TRANS_DF_iii(MOD_S, trans_msa_3r, gen_helper_msa_mod_s); 512 TRANS_DF_iii(MOD_U, trans_msa_3r, gen_helper_msa_mod_u); 513 514 TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s); 515 TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u); 516 TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s); 517 TRANS_DF_iii_b(DPADD_U, trans_msa_3r, gen_helper_msa_dpadd_u); 518 TRANS_DF_iii_b(DPSUB_S, trans_msa_3r, gen_helper_msa_dpsub_s); 519 TRANS_DF_iii_b(DPSUB_U, trans_msa_3r, gen_helper_msa_dpsub_u); 520 521 TRANS(SLD, trans_msa_3rf, gen_helper_msa_sld_df); 522 TRANS(SPLAT, trans_msa_3rf, gen_helper_msa_splat_df); 523 TRANS_DF_iii(PCKEV, trans_msa_3r, gen_helper_msa_pckev); 524 TRANS_DF_iii(PCKOD, trans_msa_3r, gen_helper_msa_pckod); 525 TRANS_DF_iii(ILVL, trans_msa_3r, gen_helper_msa_ilvl); 526 TRANS_DF_iii(ILVR, trans_msa_3r, gen_helper_msa_ilvr); 527 TRANS_DF_iii(ILVEV, trans_msa_3r, gen_helper_msa_ilvev); 528 TRANS_DF_iii(ILVOD, trans_msa_3r, gen_helper_msa_ilvod); 529 530 TRANS(VSHF, trans_msa_3rf, gen_helper_msa_vshf_df); 531 TRANS_DF_iii(SRAR, trans_msa_3r, gen_helper_msa_srar); 532 TRANS_DF_iii(SRLR, trans_msa_3r, gen_helper_msa_srlr); 533 TRANS_DF_iii_b(HADD_S, trans_msa_3r, gen_helper_msa_hadd_s); 534 TRANS_DF_iii_b(HADD_U, trans_msa_3r, gen_helper_msa_hadd_u); 535 TRANS_DF_iii_b(HSUB_S, trans_msa_3r, gen_helper_msa_hsub_s); 536 TRANS_DF_iii_b(HSUB_U, trans_msa_3r, gen_helper_msa_hsub_u); 537 538 static void gen_msa_elm_3e(DisasContext *ctx) 539 { 540 #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) 541 uint8_t source = (ctx->opcode >> 11) & 0x1f; 542 uint8_t dest = (ctx->opcode >> 6) & 0x1f; 543 TCGv telm = tcg_temp_new(); 544 TCGv_i32 tsr = tcg_const_i32(source); 545 TCGv_i32 tdt = tcg_const_i32(dest); 546 547 switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { 548 case OPC_CTCMSA: 549 gen_load_gpr(telm, source); 550 gen_helper_msa_ctcmsa(cpu_env, telm, tdt); 551 break; 552 case OPC_CFCMSA: 553 gen_helper_msa_cfcmsa(telm, cpu_env, tsr); 554 gen_store_gpr(telm, dest); 555 break; 556 case OPC_MOVE_V: 557 gen_helper_msa_move_v(cpu_env, tdt, tsr); 558 break; 559 default: 560 MIPS_INVAL("MSA instruction"); 561 gen_reserved_instruction(ctx); 562 break; 563 } 564 565 tcg_temp_free(telm); 566 tcg_temp_free_i32(tdt); 567 tcg_temp_free_i32(tsr); 568 } 569 570 static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a, 571 gen_helper_piiii *gen_msa_elm_df) 572 { 573 if (a->df < 0) { 574 return false; 575 } 576 577 if (!check_msa_enabled(ctx)) { 578 return true; 579 } 580 581 gen_msa_elm_df(cpu_env, 582 tcg_constant_i32(a->df), 583 tcg_constant_i32(a->wd), 584 tcg_constant_i32(a->ws), 585 tcg_constant_i32(a->n)); 586 587 return true; 588 } 589 590 TRANS(SLDI, trans_msa_elm, gen_helper_msa_sldi_df); 591 TRANS(SPLATI, trans_msa_elm, gen_helper_msa_splati_df); 592 TRANS(INSVE, trans_msa_elm, gen_helper_msa_insve_df); 593 594 static bool trans_msa_elm_fn(DisasContext *ctx, arg_msa_elm_df *a, 595 gen_helper_piii * const gen_msa_elm[4]) 596 { 597 if (a->df < 0 || !gen_msa_elm[a->df]) { 598 return false; 599 } 600 601 if (check_msa_enabled(ctx)) { 602 return true; 603 } 604 605 if (a->wd == 0) { 606 /* Treat as NOP. */ 607 return true; 608 } 609 610 gen_msa_elm[a->df](cpu_env, 611 tcg_constant_i32(a->wd), 612 tcg_constant_i32(a->ws), 613 tcg_constant_i32(a->n)); 614 615 return true; 616 } 617 618 #if defined(TARGET_MIPS64) 619 #define NULL_IF_MIPS32(function) function 620 #else 621 #define NULL_IF_MIPS32(function) NULL 622 #endif 623 624 static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a) 625 { 626 static gen_helper_piii * const gen_msa_copy_u[4] = { 627 gen_helper_msa_copy_u_b, gen_helper_msa_copy_u_h, 628 NULL_IF_MIPS32(gen_helper_msa_copy_u_w), NULL 629 }; 630 631 return trans_msa_elm_fn(ctx, a, gen_msa_copy_u); 632 } 633 634 static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) 635 { 636 #define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) 637 uint8_t ws = (ctx->opcode >> 11) & 0x1f; 638 uint8_t wd = (ctx->opcode >> 6) & 0x1f; 639 640 TCGv_i32 tws = tcg_const_i32(ws); 641 TCGv_i32 twd = tcg_const_i32(wd); 642 TCGv_i32 tn = tcg_const_i32(n); 643 644 switch (MASK_MSA_ELM(ctx->opcode)) { 645 case OPC_COPY_S_df: 646 case OPC_INSERT_df: 647 #if !defined(TARGET_MIPS64) 648 /* Double format valid only for MIPS64 */ 649 if (df == DF_DOUBLE) { 650 gen_reserved_instruction(ctx); 651 break; 652 } 653 #endif 654 switch (MASK_MSA_ELM(ctx->opcode)) { 655 case OPC_COPY_S_df: 656 if (likely(wd != 0)) { 657 switch (df) { 658 case DF_BYTE: 659 gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn); 660 break; 661 case DF_HALF: 662 gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn); 663 break; 664 case DF_WORD: 665 gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn); 666 break; 667 #if defined(TARGET_MIPS64) 668 case DF_DOUBLE: 669 gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn); 670 break; 671 #endif 672 default: 673 assert(0); 674 } 675 } 676 break; 677 case OPC_INSERT_df: 678 switch (df) { 679 case DF_BYTE: 680 gen_helper_msa_insert_b(cpu_env, twd, tws, tn); 681 break; 682 case DF_HALF: 683 gen_helper_msa_insert_h(cpu_env, twd, tws, tn); 684 break; 685 case DF_WORD: 686 gen_helper_msa_insert_w(cpu_env, twd, tws, tn); 687 break; 688 #if defined(TARGET_MIPS64) 689 case DF_DOUBLE: 690 gen_helper_msa_insert_d(cpu_env, twd, tws, tn); 691 break; 692 #endif 693 default: 694 assert(0); 695 } 696 break; 697 } 698 break; 699 default: 700 MIPS_INVAL("MSA instruction"); 701 gen_reserved_instruction(ctx); 702 } 703 tcg_temp_free_i32(twd); 704 tcg_temp_free_i32(tws); 705 tcg_temp_free_i32(tn); 706 } 707 708 static void gen_msa_elm(DisasContext *ctx) 709 { 710 uint8_t dfn = (ctx->opcode >> 16) & 0x3f; 711 uint32_t df = 0, n = 0; 712 713 if ((dfn & 0x30) == 0x00) { 714 n = dfn & 0x0f; 715 df = DF_BYTE; 716 } else if ((dfn & 0x38) == 0x20) { 717 n = dfn & 0x07; 718 df = DF_HALF; 719 } else if ((dfn & 0x3c) == 0x30) { 720 n = dfn & 0x03; 721 df = DF_WORD; 722 } else if ((dfn & 0x3e) == 0x38) { 723 n = dfn & 0x01; 724 df = DF_DOUBLE; 725 } else if (dfn == 0x3E) { 726 /* CTCMSA, CFCMSA, MOVE.V */ 727 gen_msa_elm_3e(ctx); 728 return; 729 } else { 730 gen_reserved_instruction(ctx); 731 return; 732 } 733 734 gen_msa_elm_df(ctx, df, n); 735 } 736 737 TRANS(FCAF, trans_msa_3rf, gen_helper_msa_fcaf_df); 738 TRANS(FCUN, trans_msa_3rf, gen_helper_msa_fcun_df); 739 TRANS(FCEQ, trans_msa_3rf, gen_helper_msa_fceq_df); 740 TRANS(FCUEQ, trans_msa_3rf, gen_helper_msa_fcueq_df); 741 TRANS(FCLT, trans_msa_3rf, gen_helper_msa_fclt_df); 742 TRANS(FCULT, trans_msa_3rf, gen_helper_msa_fcult_df); 743 TRANS(FCLE, trans_msa_3rf, gen_helper_msa_fcle_df); 744 TRANS(FCULE, trans_msa_3rf, gen_helper_msa_fcule_df); 745 TRANS(FSAF, trans_msa_3rf, gen_helper_msa_fsaf_df); 746 TRANS(FSUN, trans_msa_3rf, gen_helper_msa_fsun_df); 747 TRANS(FSEQ, trans_msa_3rf, gen_helper_msa_fseq_df); 748 TRANS(FSUEQ, trans_msa_3rf, gen_helper_msa_fsueq_df); 749 TRANS(FSLT, trans_msa_3rf, gen_helper_msa_fslt_df); 750 TRANS(FSULT, trans_msa_3rf, gen_helper_msa_fsult_df); 751 TRANS(FSLE, trans_msa_3rf, gen_helper_msa_fsle_df); 752 TRANS(FSULE, trans_msa_3rf, gen_helper_msa_fsule_df); 753 754 TRANS(FADD, trans_msa_3rf, gen_helper_msa_fadd_df); 755 TRANS(FSUB, trans_msa_3rf, gen_helper_msa_fsub_df); 756 TRANS(FMUL, trans_msa_3rf, gen_helper_msa_fmul_df); 757 TRANS(FDIV, trans_msa_3rf, gen_helper_msa_fdiv_df); 758 TRANS(FMADD, trans_msa_3rf, gen_helper_msa_fmadd_df); 759 TRANS(FMSUB, trans_msa_3rf, gen_helper_msa_fmsub_df); 760 TRANS(FEXP2, trans_msa_3rf, gen_helper_msa_fexp2_df); 761 TRANS(FEXDO, trans_msa_3rf, gen_helper_msa_fexdo_df); 762 TRANS(FTQ, trans_msa_3rf, gen_helper_msa_ftq_df); 763 TRANS(FMIN, trans_msa_3rf, gen_helper_msa_fmin_df); 764 TRANS(FMIN_A, trans_msa_3rf, gen_helper_msa_fmin_a_df); 765 TRANS(FMAX, trans_msa_3rf, gen_helper_msa_fmax_df); 766 TRANS(FMAX_A, trans_msa_3rf, gen_helper_msa_fmax_a_df); 767 768 TRANS(FCOR, trans_msa_3rf, gen_helper_msa_fcor_df); 769 TRANS(FCUNE, trans_msa_3rf, gen_helper_msa_fcune_df); 770 TRANS(FCNE, trans_msa_3rf, gen_helper_msa_fcne_df); 771 TRANS(MUL_Q, trans_msa_3rf, gen_helper_msa_mul_q_df); 772 TRANS(MADD_Q, trans_msa_3rf, gen_helper_msa_madd_q_df); 773 TRANS(MSUB_Q, trans_msa_3rf, gen_helper_msa_msub_q_df); 774 TRANS(FSOR, trans_msa_3rf, gen_helper_msa_fsor_df); 775 TRANS(FSUNE, trans_msa_3rf, gen_helper_msa_fsune_df); 776 TRANS(FSNE, trans_msa_3rf, gen_helper_msa_fsne_df); 777 TRANS(MULR_Q, trans_msa_3rf, gen_helper_msa_mulr_q_df); 778 TRANS(MADDR_Q, trans_msa_3rf, gen_helper_msa_maddr_q_df); 779 TRANS(MSUBR_Q, trans_msa_3rf, gen_helper_msa_msubr_q_df); 780 781 static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a, 782 gen_helper_pii *gen_msa_2r) 783 { 784 if (!check_msa_enabled(ctx)) { 785 return true; 786 } 787 788 gen_msa_2r(cpu_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws)); 789 790 return true; 791 } 792 793 TRANS_DF_ii(PCNT, trans_msa_2r, gen_helper_msa_pcnt); 794 TRANS_DF_ii(NLOC, trans_msa_2r, gen_helper_msa_nloc); 795 TRANS_DF_ii(NLZC, trans_msa_2r, gen_helper_msa_nlzc); 796 797 static bool trans_FILL(DisasContext *ctx, arg_msa_r *a) 798 { 799 if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) { 800 /* Double format valid only for MIPS64 */ 801 return false; 802 } 803 804 if (!check_msa_enabled(ctx)) { 805 return true; 806 } 807 808 gen_helper_msa_fill_df(cpu_env, 809 tcg_constant_i32(a->df), 810 tcg_constant_i32(a->wd), 811 tcg_constant_i32(a->ws)); 812 813 return true; 814 } 815 816 static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r *a, 817 gen_helper_piii *gen_msa_2rf) 818 { 819 if (!check_msa_enabled(ctx)) { 820 return true; 821 } 822 823 gen_msa_2rf(cpu_env, 824 tcg_constant_i32(a->df), 825 tcg_constant_i32(a->wd), 826 tcg_constant_i32(a->ws)); 827 828 return true; 829 } 830 831 TRANS(FCLASS, trans_msa_2rf, gen_helper_msa_fclass_df); 832 TRANS(FTRUNC_S, trans_msa_2rf, gen_helper_msa_fclass_df); 833 TRANS(FTRUNC_U, trans_msa_2rf, gen_helper_msa_ftrunc_s_df); 834 TRANS(FSQRT, trans_msa_2rf, gen_helper_msa_fsqrt_df); 835 TRANS(FRSQRT, trans_msa_2rf, gen_helper_msa_frsqrt_df); 836 TRANS(FRCP, trans_msa_2rf, gen_helper_msa_frcp_df); 837 TRANS(FRINT, trans_msa_2rf, gen_helper_msa_frint_df); 838 TRANS(FLOG2, trans_msa_2rf, gen_helper_msa_flog2_df); 839 TRANS(FEXUPL, trans_msa_2rf, gen_helper_msa_fexupl_df); 840 TRANS(FEXUPR, trans_msa_2rf, gen_helper_msa_fexupr_df); 841 TRANS(FFQL, trans_msa_2rf, gen_helper_msa_ffql_df); 842 TRANS(FFQR, trans_msa_2rf, gen_helper_msa_ffqr_df); 843 TRANS(FTINT_S, trans_msa_2rf, gen_helper_msa_ftint_s_df); 844 TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df); 845 TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); 846 TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); 847 848 static bool trans_MSA(DisasContext *ctx, arg_MSA *a) 849 { 850 uint32_t opcode = ctx->opcode; 851 852 if (!check_msa_enabled(ctx)) { 853 return true; 854 } 855 856 switch (MASK_MSA_MINOR(opcode)) { 857 case OPC_MSA_ELM: 858 gen_msa_elm(ctx); 859 break; 860 default: 861 MIPS_INVAL("MSA instruction"); 862 gen_reserved_instruction(ctx); 863 break; 864 } 865 866 return true; 867 } 868 869 static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, 870 gen_helper_piv *gen_msa_ldst) 871 { 872 TCGv taddr; 873 874 if (!check_msa_enabled(ctx)) { 875 return true; 876 } 877 878 taddr = tcg_temp_new(); 879 880 gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df); 881 gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr); 882 883 tcg_temp_free(taddr); 884 885 return true; 886 } 887 888 TRANS_DF_iv(LD, trans_msa_ldst, gen_helper_msa_ld); 889 TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st); 890 891 static bool trans_LSA(DisasContext *ctx, arg_r *a) 892 { 893 return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); 894 } 895 896 static bool trans_DLSA(DisasContext *ctx, arg_r *a) 897 { 898 if (TARGET_LONG_BITS != 64) { 899 return false; 900 } 901 return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); 902 } 903