hw/intc/loongson_ipi: Add load and save interface with ipi_common class

Add pre_save and post_load interfaces with ipi_common class, here only
framework ipi_common adds these interfaces. The defaile

hw/intc/loongson_ipi: Add load and save interface with ipi_common class

Add pre_save and post_load interfaces with ipi_common class, here only
framework ipi_common adds these interfaces. The defailed implementation
is LoongArchIPI child device in later.

Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20250606063033.2557365-5-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_ipi: Add kernel irqchip realize function

Function kvm_ipi_realize() is added if kvm_irqchip_in_kernel() return true.
It is to create and initialize IPI device in kernel mode.

Revi

hw/intc/loongarch_ipi: Add kernel irqchip realize function

Function kvm_ipi_realize() is added if kvm_irqchip_in_kernel() return true.
It is to create and initialize IPI device in kernel mode.

Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20250606063033.2557365-4-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_extioi: Add kernel irqchip save and restore function

Add save and store funtction if kvm_irqchip_in_kernel() return true,
it is to get and set ExtIOI irqchip state from KVM kernel.

hw/intc/loongarch_extioi: Add kernel irqchip save and restore function

Add save and store funtction if kvm_irqchip_in_kernel() return true,
it is to get and set ExtIOI irqchip state from KVM kernel.

Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20250606063033.2557365-3-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_extioi: Add kernel irqchip realize function

Function kvm_extioi_realize() is added if kvm_irqchip_in_kernel is
set. It is to create and initialize ExtIOI device in kernel mode.

Re

hw/intc/loongarch_extioi: Add kernel irqchip realize function

Function kvm_extioi_realize() is added if kvm_irqchip_in_kernel is
set. It is to create and initialize ExtIOI device in kernel mode.

Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20250606063033.2557365-2-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/arm_gic: introduce a first-cpu-index property

This introduces a first-cpu-index property to the arm-gic, as some SOCs
could have two separate GIC (ie: the zynqmp).

Signed-off-by: Clément Ch

hw/intc/arm_gic: introduce a first-cpu-index property

This introduces a first-cpu-index property to the arm-gic, as some SOCs
could have two separate GIC (ie: the zynqmp).

Signed-off-by: Clément Chigot <chigot@adacore.com>
Message-id: 20250526085523.809003-3-chigot@adacore.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: slightly expanded comment documenting GIC property]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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hw/intc/loongarch_pch: Convert to little endian with ID register

With PCH ID register, it is defined as union type as follows:
union LoongArchPIC_ID {
struct {
uint8_t _reserved_0[3];

hw/intc/loongarch_pch: Convert to little endian with ID register

With PCH ID register, it is defined as union type as follows:
union LoongArchPIC_ID {
struct {
uint8_t _reserved_0[3];
uint8_t id;
uint8_t version;
uint8_t _reserved_1;
uint8_t irq_num;
uint8_t _reserved_2;
} QEMU_PACKED desc;
uint64_t data;
}

And with pch driver in virt machine irq_number is parsed with little
endian method:
vec_count = ((readq(priv->base) >> 48) & 0xff) + 1

So the value of ID register should be converted to little endian.
With this patch, linux kernel passes to run on S390 big endian host
machine with TCG method.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250604065502.1114098-3-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/aspeed Fix coding style

Fix coding style issues from checkpatch.pl.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.ker

hw/intc/aspeed Fix coding style

Fix coding style issues from checkpatch.pl.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250522023305.2486536-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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hw/intc/aspeed: Set impl.min_access_size to 4

This patch explicitly sets ".impl.min_access_size = 4" to match the
declared ".valid.min_access_size = 4", enforcing stricter access size
checking and p

hw/intc/aspeed: Set impl.min_access_size to 4

This patch explicitly sets ".impl.min_access_size = 4" to match the
declared ".valid.min_access_size = 4", enforcing stricter access size
checking and preventing inconsistent partial accesses to the interrupt
controller registers.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250522023305.2486536-2-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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hw/arm: Replace TABs for spaces in OMAP board and device code

In hw/arm and include/hw/arm, some source files for the OMAP SoC
and the sx1 boards that are our only remaining OMAP boards still
have h

hw/arm: Replace TABs for spaces in OMAP board and device code

In hw/arm and include/hw/arm, some source files for the OMAP SoC
and the sx1 boards that are our only remaining OMAP boards still
have hard-coded tabs (almost entirely used for the indent on
inline comments, not for actual code indent).

Replace the tabs with spaces using vim :retab. I used 4 spaces
except in some defines and comments where I tried to put
everything aligned in the same column for better readability.

This commit is a purely whitespace-only change.

Signed-off-by: Santiago Monserrat Campanello <santimonserr@gmail.com>
Message-id: 20250505131130.82206-1-santimonserr@gmail.com
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/373
[PMM: expanded commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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hw/intc/loongarch_pch: Merge three memory region into one

Since memory region iomem supports memory access size with 1/2/4/8,
it can be used for memory region iomem8 and iomem32_high. Now remove
mem

hw/intc/loongarch_pch: Merge three memory region into one

Since memory region iomem supports memory access size with 1/2/4/8,
it can be used for memory region iomem8 and iomem32_high. Now remove
memory region iomem8 and iomem32_high, merge them into iomem together.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023754.1877445-5-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Set flexible memory access size with iomem region

The original iomem region only supports 4 bytes access size, set it ok
with 1/2/4/8 bytes. Also unaligned memory access is no

hw/intc/loongarch_pch: Set flexible memory access size with iomem region

The original iomem region only supports 4 bytes access size, set it ok
with 1/2/4/8 bytes. Also unaligned memory access is not supported.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023754.1877445-4-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Rename memory region iomem32_low with iomem

Rename memory region iomem32_low with iomem, also change ops name
as follows:
loongarch_pch_pic_reg32_low_ops --> loongarch_pch_

hw/intc/loongarch_pch: Rename memory region iomem32_low with iomem

Rename memory region iomem32_low with iomem, also change ops name
as follows:
loongarch_pch_pic_reg32_low_ops --> loongarch_pch_pic_ops
loongarch_pch_pic_low_readw --> loongarch_pch_pic_read
loongarch_pch_pic_low_writew --> loongarch_pch_pic_write

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023754.1877445-3-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Use unified trace event for memory region ops

Add trace event trace_loongarch_pch_pic_read(), replaces the following
three events:
trace_loongarch_pch_pic_low_readw()
trac

hw/intc/loongarch_pch: Use unified trace event for memory region ops

Add trace event trace_loongarch_pch_pic_read(), replaces the following
three events:
trace_loongarch_pch_pic_low_readw()
trace_loongarch_pch_pic_high_readw()
trace_loongarch_pch_pic_readb()
The similiar with write trace event.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023754.1877445-2-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Use generic write callback for iomem8 region

Add iomem8 region register write operation emulation in generic write
function loongarch_pch_pic_write(), and use this function fo

hw/intc/loongarch_pch: Use generic write callback for iomem8 region

Add iomem8 region register write operation emulation in generic write
function loongarch_pch_pic_write(), and use this function for iomem8
region.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023754.1877445-1-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Use generic write callback for iomem32_high region

Add iomem32_high region register write operation emulation in generic
write function loongarch_pch_pic_write(), and use this

hw/intc/loongarch_pch: Use generic write callback for iomem32_high region

Add iomem32_high region register write operation emulation in generic
write function loongarch_pch_pic_write(), and use this function for
iomem32_high region.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023148.1877287-12-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Use generic write callback for iomem32_low region

For memory region iomem32_low, generic write callback is used.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: So

hw/intc/loongarch_pch: Use generic write callback for iomem32_low region

For memory region iomem32_low, generic write callback is used.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023148.1877287-11-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Use generic read callback for iomem8 region

Add iomem8 region register read operation emulation in generic read
function loongarch_pch_pic_read(), and use this function for io

hw/intc/loongarch_pch: Use generic read callback for iomem8 region

Add iomem8 region register read operation emulation in generic read
function loongarch_pch_pic_read(), and use this function for iomem8
region.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023148.1877287-10-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Use generic read callback for iomem32_high region

Add register read operation emulation in generic read function
loongarch_pch_pic_read(), and use this function for iomem32_hi

hw/intc/loongarch_pch: Use generic read callback for iomem32_high region

Add register read operation emulation in generic read function
loongarch_pch_pic_read(), and use this function for iomem32_high region.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023148.1877287-9-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Use generic read callback for iomem32_low region

For memory region iomem32_low, generic read callback is used.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song

hw/intc/loongarch_pch: Use generic read callback for iomem32_low region

For memory region iomem32_low, generic read callback is used.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023148.1877287-8-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Discard write operation with ISR register

With the latest 7A1000 user manual, interrupt status register ISR is
read only. Here discard write operation with ISR register.

Sign

hw/intc/loongarch_pch: Discard write operation with ISR register

With the latest 7A1000 user manual, interrupt status register ISR is
read only. Here discard write operation with ISR register.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023148.1877287-7-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Use relative address in MemoryRegionOps

Parameter address for read and write callback in MemoryRegionOps is
relative offset with base address of this MemoryRegionOps. It can
b

hw/intc/loongarch_pch: Use relative address in MemoryRegionOps

Parameter address for read and write callback in MemoryRegionOps is
relative offset with base address of this MemoryRegionOps. It can
be directly used as offset and offset calculation can be removed.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023148.1877287-6-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Set version information at initial stage

Register PCH_PIC_INT_ID constains version and supported irq number
information, and it is read only register. The detailed value can
b

hw/intc/loongarch_pch: Set version information at initial stage

Register PCH_PIC_INT_ID constains version and supported irq number
information, and it is read only register. The detailed value can
be set at initial stage, rather than read callback.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023148.1877287-5-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Remove some duplicate macro

The meaning of macro definition STATUS_LO_START is simliar with
PCH_PIC_INT_STATUS, only that offset is different, the same for
macro POL_LO_START.

hw/intc/loongarch_pch: Remove some duplicate macro

The meaning of macro definition STATUS_LO_START is simliar with
PCH_PIC_INT_STATUS, only that offset is different, the same for
macro POL_LO_START. Now remove these duplicated macro definitions.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023148.1877287-4-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Modify register name PCH_PIC_xxx_OFFSET with PCH_PIC_xxx

Macro PCH_PIC_HTMSI_VEC_OFFSET and PCH_PIC_ROUTE_ENTRY_OFFSET is renamed
as PCH_PIC_HTMSI_VEC and PCH_PIC_ROUTE_ENTRY

hw/intc/loongarch_pch: Modify register name PCH_PIC_xxx_OFFSET with PCH_PIC_xxx

Macro PCH_PIC_HTMSI_VEC_OFFSET and PCH_PIC_ROUTE_ENTRY_OFFSET is renamed
as PCH_PIC_HTMSI_VEC and PCH_PIC_ROUTE_ENTRY separately, it is easier to
understand.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023148.1877287-3-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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hw/intc/loongarch_pch: Modify name of some registers

For some registers with width 8 bytes, its name is something like
PCH_PIC_INT_ID_LO and PCH_PIC_INT_ID_HI. From hardware manual,
register name is

hw/intc/loongarch_pch: Modify name of some registers

For some registers with width 8 bytes, its name is something like
PCH_PIC_INT_ID_LO and PCH_PIC_INT_ID_HI. From hardware manual,
register name is PCH_PIC_INT_ID instead. Here name PCH_PIC_INT_ID
is used, and PCH_PIC_INT_ID + 4 is used for PCH_PIC_INT_ID_HI.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023148.1877287-2-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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