1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU Loongson 7A1000 I/O interrupt controller. 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/bitops.h" 10 #include "qemu/log.h" 11 #include "hw/irq.h" 12 #include "hw/intc/loongarch_pch_pic.h" 13 #include "trace.h" 14 #include "qapi/error.h" 15 16 static void pch_pic_update_irq(LoongArchPICCommonState *s, uint64_t mask, 17 int level) 18 { 19 uint64_t val; 20 int irq; 21 22 if (level) { 23 val = mask & s->intirr & ~s->int_mask; 24 if (val) { 25 irq = ctz64(val); 26 s->intisr |= MAKE_64BIT_MASK(irq, 1); 27 qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 1); 28 } 29 } else { 30 /* 31 * intirr means requested pending irq 32 * do not clear pending irq for edge-triggered on lowering edge 33 */ 34 val = mask & s->intisr & ~s->intirr; 35 if (val) { 36 irq = ctz64(val); 37 s->intisr &= ~MAKE_64BIT_MASK(irq, 1); 38 qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 0); 39 } 40 } 41 } 42 43 static void pch_pic_irq_handler(void *opaque, int irq, int level) 44 { 45 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque); 46 uint64_t mask = 1ULL << irq; 47 48 assert(irq < s->irq_num); 49 trace_loongarch_pch_pic_irq_handler(irq, level); 50 51 if (s->intedge & mask) { 52 /* Edge triggered */ 53 if (level) { 54 if ((s->last_intirr & mask) == 0) { 55 /* marked pending on a rising edge */ 56 s->intirr |= mask; 57 } 58 s->last_intirr |= mask; 59 } else { 60 s->last_intirr &= ~mask; 61 } 62 } else { 63 /* Level triggered */ 64 if (level) { 65 s->intirr |= mask; 66 s->last_intirr |= mask; 67 } else { 68 s->intirr &= ~mask; 69 s->last_intirr &= ~mask; 70 } 71 } 72 pch_pic_update_irq(s, mask, level); 73 } 74 75 static uint64_t pch_pic_read(void *opaque, hwaddr addr, uint64_t field_mask) 76 { 77 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque); 78 uint64_t val = 0; 79 uint32_t offset; 80 81 offset = addr & 7; 82 addr -= offset; 83 switch (addr) { 84 case PCH_PIC_INT_ID: 85 val = s->id.data; 86 break; 87 case PCH_PIC_INT_MASK: 88 val = s->int_mask; 89 break; 90 case PCH_PIC_INT_EDGE: 91 val = s->intedge; 92 break; 93 case PCH_PIC_HTMSI_EN: 94 val = s->htmsi_en; 95 break; 96 case PCH_PIC_AUTO_CTRL0: 97 case PCH_PIC_AUTO_CTRL1: 98 /* PCH PIC connect to EXTIOI always, discard auto_ctrl access */ 99 break; 100 case PCH_PIC_INT_STATUS: 101 val = s->intisr & (~s->int_mask); 102 break; 103 case PCH_PIC_INT_POL: 104 val = s->int_polarity; 105 break; 106 case PCH_PIC_HTMSI_VEC ... PCH_PIC_HTMSI_VEC_END: 107 val = *(uint64_t *)(s->htmsi_vector + addr - PCH_PIC_HTMSI_VEC); 108 break; 109 case PCH_PIC_ROUTE_ENTRY ... PCH_PIC_ROUTE_ENTRY_END: 110 val = *(uint64_t *)(s->route_entry + addr - PCH_PIC_ROUTE_ENTRY); 111 break; 112 default: 113 qemu_log_mask(LOG_GUEST_ERROR, 114 "pch_pic_read: Bad address 0x%"PRIx64"\n", addr); 115 break; 116 } 117 118 return (val >> (offset * 8)) & field_mask; 119 } 120 121 static void pch_pic_write(void *opaque, hwaddr addr, uint64_t value, 122 uint64_t field_mask) 123 { 124 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque); 125 uint32_t offset; 126 uint64_t old, mask, data; 127 128 offset = addr & 7; 129 addr -= offset; 130 mask = field_mask << (offset * 8); 131 data = (value & field_mask) << (offset * 8); 132 switch (addr) { 133 case PCH_PIC_INT_MASK: 134 old = s->int_mask; 135 s->int_mask = (old & ~mask) | data; 136 if (old & ~data) { 137 pch_pic_update_irq(s, old & ~data, 1); 138 } 139 140 if (~old & data) { 141 pch_pic_update_irq(s, ~old & data, 0); 142 } 143 break; 144 case PCH_PIC_INT_EDGE: 145 s->intedge = (s->intedge & ~mask) | data; 146 break; 147 case PCH_PIC_INT_CLEAR: 148 if (s->intedge & data) { 149 s->intirr &= ~data; 150 pch_pic_update_irq(s, data, 0); 151 s->intisr &= ~data; 152 } 153 break; 154 case PCH_PIC_HTMSI_EN: 155 s->htmsi_en = (s->htmsi_en & ~mask) | data; 156 break; 157 case PCH_PIC_AUTO_CTRL0: 158 case PCH_PIC_AUTO_CTRL1: 159 /* Discard auto_ctrl access */ 160 break; 161 case PCH_PIC_INT_POL: 162 s->int_polarity = (s->int_polarity & ~mask) | data; 163 break; 164 default: 165 qemu_log_mask(LOG_GUEST_ERROR, 166 "pch_pic_write: Bad address 0x%"PRIx64"\n", addr); 167 break; 168 } 169 } 170 171 static uint64_t loongarch_pch_pic_read(void *opaque, hwaddr addr, 172 unsigned size) 173 { 174 uint64_t val = 0; 175 176 switch (size) { 177 case 1: 178 val = pch_pic_read(opaque, addr, UCHAR_MAX); 179 break; 180 case 2: 181 val = pch_pic_read(opaque, addr, USHRT_MAX); 182 break; 183 case 4: 184 val = pch_pic_read(opaque, addr, UINT_MAX); 185 break; 186 case 8: 187 val = pch_pic_read(opaque, addr, UINT64_MAX); 188 break; 189 default: 190 qemu_log_mask(LOG_GUEST_ERROR, 191 "loongarch_pch_pic_read: Bad size %d\n", size); 192 break; 193 } 194 195 return val; 196 } 197 198 static void loongarch_pch_pic_write(void *opaque, hwaddr addr, 199 uint64_t value, unsigned size) 200 { 201 switch (size) { 202 case 1: 203 pch_pic_write(opaque, addr, value, UCHAR_MAX); 204 break; 205 case 2: 206 pch_pic_write(opaque, addr, value, USHRT_MAX); 207 break; 208 break; 209 case 4: 210 pch_pic_write(opaque, addr, value, UINT_MAX); 211 break; 212 case 8: 213 pch_pic_write(opaque, addr, value, UINT64_MAX); 214 break; 215 default: 216 qemu_log_mask(LOG_GUEST_ERROR, 217 "loongarch_pch_pic_write: Bad size %d\n", size); 218 break; 219 } 220 } 221 222 static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr, 223 unsigned size) 224 { 225 uint64_t val; 226 227 val = loongarch_pch_pic_read(opaque, addr, size); 228 trace_loongarch_pch_pic_low_readw(size, addr, val); 229 return val; 230 } 231 232 static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr, 233 uint64_t value, unsigned size) 234 { 235 trace_loongarch_pch_pic_low_writew(size, addr, value); 236 loongarch_pch_pic_write(opaque, addr, value, size); 237 } 238 239 static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr, 240 unsigned size) 241 { 242 uint64_t val; 243 244 addr += PCH_PIC_INT_STATUS; 245 val = loongarch_pch_pic_read(opaque, addr, size); 246 trace_loongarch_pch_pic_high_readw(size, addr, val); 247 return val; 248 } 249 250 static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr, 251 uint64_t value, unsigned size) 252 { 253 addr += PCH_PIC_INT_STATUS; 254 trace_loongarch_pch_pic_high_writew(size, addr, value); 255 loongarch_pch_pic_write(opaque, addr, value, size); 256 } 257 258 static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr, 259 unsigned size) 260 { 261 uint64_t val; 262 263 addr += PCH_PIC_ROUTE_ENTRY; 264 val = loongarch_pch_pic_read(opaque, addr, size); 265 trace_loongarch_pch_pic_readb(size, addr, val); 266 return val; 267 } 268 269 static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr, 270 uint64_t data, unsigned size) 271 { 272 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque); 273 int32_t offset_tmp; 274 275 addr += PCH_PIC_ROUTE_ENTRY; 276 trace_loongarch_pch_pic_writeb(size, addr, data); 277 278 switch (addr) { 279 case PCH_PIC_HTMSI_VEC ... PCH_PIC_HTMSI_VEC_END: 280 offset_tmp = addr - PCH_PIC_HTMSI_VEC; 281 if (offset_tmp >= 0 && offset_tmp < 64) { 282 s->htmsi_vector[offset_tmp] = (uint8_t)(data & 0xff); 283 } 284 break; 285 case PCH_PIC_ROUTE_ENTRY ... PCH_PIC_ROUTE_ENTRY_END: 286 offset_tmp = addr - PCH_PIC_ROUTE_ENTRY; 287 if (offset_tmp >= 0 && offset_tmp < 64) { 288 s->route_entry[offset_tmp] = (uint8_t)(data & 0xff); 289 } 290 break; 291 default: 292 break; 293 } 294 } 295 296 static const MemoryRegionOps loongarch_pch_pic_reg32_low_ops = { 297 .read = loongarch_pch_pic_low_readw, 298 .write = loongarch_pch_pic_low_writew, 299 .valid = { 300 .min_access_size = 4, 301 .max_access_size = 8, 302 }, 303 .impl = { 304 .min_access_size = 4, 305 .max_access_size = 4, 306 }, 307 .endianness = DEVICE_LITTLE_ENDIAN, 308 }; 309 310 static const MemoryRegionOps loongarch_pch_pic_reg32_high_ops = { 311 .read = loongarch_pch_pic_high_readw, 312 .write = loongarch_pch_pic_high_writew, 313 .valid = { 314 .min_access_size = 4, 315 .max_access_size = 8, 316 }, 317 .impl = { 318 .min_access_size = 4, 319 .max_access_size = 4, 320 }, 321 .endianness = DEVICE_LITTLE_ENDIAN, 322 }; 323 324 static const MemoryRegionOps loongarch_pch_pic_reg8_ops = { 325 .read = loongarch_pch_pic_readb, 326 .write = loongarch_pch_pic_writeb, 327 .valid = { 328 .min_access_size = 1, 329 .max_access_size = 1, 330 }, 331 .impl = { 332 .min_access_size = 1, 333 .max_access_size = 1, 334 }, 335 .endianness = DEVICE_LITTLE_ENDIAN, 336 }; 337 338 static void loongarch_pic_reset_hold(Object *obj, ResetType type) 339 { 340 LoongarchPICClass *lpc = LOONGARCH_PIC_GET_CLASS(obj); 341 342 if (lpc->parent_phases.hold) { 343 lpc->parent_phases.hold(obj, type); 344 } 345 } 346 347 static void loongarch_pic_realize(DeviceState *dev, Error **errp) 348 { 349 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev); 350 LoongarchPICClass *lpc = LOONGARCH_PIC_GET_CLASS(dev); 351 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 352 Error *local_err = NULL; 353 354 lpc->parent_realize(dev, &local_err); 355 if (local_err) { 356 error_propagate(errp, local_err); 357 return; 358 } 359 360 qdev_init_gpio_out(dev, s->parent_irq, s->irq_num); 361 qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num); 362 memory_region_init_io(&s->iomem32_low, OBJECT(dev), 363 &loongarch_pch_pic_reg32_low_ops, 364 s, PCH_PIC_NAME(.reg32_part1), 0x100); 365 memory_region_init_io(&s->iomem8, OBJECT(dev), &loongarch_pch_pic_reg8_ops, 366 s, PCH_PIC_NAME(.reg8), 0x2a0); 367 memory_region_init_io(&s->iomem32_high, OBJECT(dev), 368 &loongarch_pch_pic_reg32_high_ops, 369 s, PCH_PIC_NAME(.reg32_part2), 0xc60); 370 sysbus_init_mmio(sbd, &s->iomem32_low); 371 sysbus_init_mmio(sbd, &s->iomem8); 372 sysbus_init_mmio(sbd, &s->iomem32_high); 373 374 } 375 376 static void loongarch_pic_class_init(ObjectClass *klass, const void *data) 377 { 378 DeviceClass *dc = DEVICE_CLASS(klass); 379 LoongarchPICClass *lpc = LOONGARCH_PIC_CLASS(klass); 380 ResettableClass *rc = RESETTABLE_CLASS(klass); 381 382 resettable_class_set_parent_phases(rc, NULL, loongarch_pic_reset_hold, 383 NULL, &lpc->parent_phases); 384 device_class_set_parent_realize(dc, loongarch_pic_realize, 385 &lpc->parent_realize); 386 } 387 388 static const TypeInfo loongarch_pic_types[] = { 389 { 390 .name = TYPE_LOONGARCH_PIC, 391 .parent = TYPE_LOONGARCH_PIC_COMMON, 392 .instance_size = sizeof(LoongarchPICState), 393 .class_size = sizeof(LoongarchPICClass), 394 .class_init = loongarch_pic_class_init, 395 } 396 }; 397 398 DEFINE_TYPES(loongarch_pic_types) 399