1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * LoongArch 7A1000 I/O interrupt controller definitions 4 * Copyright (c) 2024 Loongson Technology Corporation Limited 5 */ 6 7 #ifndef HW_LOONGARCH_PIC_COMMON_H 8 #define HW_LOONGARCH_PIC_COMMON_H 9 10 #include "hw/pci-host/ls7a.h" 11 #include "hw/sysbus.h" 12 13 #define PCH_PIC_INT_ID_VAL 0x7000000UL 14 #define PCH_PIC_INT_ID_VER 0x1UL 15 #define PCH_PIC_INT_ID 0x00 16 #define PCH_PIC_INT_MASK 0x20 17 #define PCH_PIC_HTMSI_EN 0x40 18 #define PCH_PIC_INT_EDGE 0x60 19 #define PCH_PIC_INT_CLEAR 0x80 20 #define PCH_PIC_AUTO_CTRL0 0xc0 21 #define PCH_PIC_AUTO_CTRL1 0xe0 22 #define PCH_PIC_ROUTE_ENTRY 0x100 23 #define PCH_PIC_ROUTE_ENTRY_END 0x13f 24 #define PCH_PIC_HTMSI_VEC 0x200 25 #define PCH_PIC_HTMSI_VEC_END 0x23f 26 #define PCH_PIC_INT_STATUS 0x3a0 27 #define PCH_PIC_INT_POL 0x3e0 28 29 #define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common" 30 OBJECT_DECLARE_TYPE(LoongArchPICCommonState, 31 LoongArchPICCommonClass, LOONGARCH_PIC_COMMON) 32 33 struct LoongArchPICCommonState { 34 SysBusDevice parent_obj; 35 36 qemu_irq parent_irq[64]; 37 uint64_t int_mask; /* 0x020 interrupt mask register */ 38 uint64_t htmsi_en; /* 0x040 1=msi */ 39 uint64_t intedge; /* 0x060 edge=1 level=0 */ 40 uint64_t intclr; /* 0x080 clean edge int, set 1 clean, 0 noused */ 41 uint64_t auto_crtl0; /* 0x0c0 */ 42 uint64_t auto_crtl1; /* 0x0e0 */ 43 uint64_t last_intirr; /* edge detection */ 44 uint64_t intirr; /* 0x380 interrupt request register */ 45 uint64_t intisr; /* 0x3a0 interrupt service register */ 46 /* 47 * 0x3e0 interrupt level polarity selection 48 * register 0 for high level trigger 49 */ 50 uint64_t int_polarity; 51 52 uint8_t route_entry[64]; /* 0x100 - 0x138 */ 53 uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */ 54 55 MemoryRegion iomem32_low; 56 MemoryRegion iomem32_high; 57 MemoryRegion iomem8; 58 unsigned int irq_num; 59 }; 60 61 struct LoongArchPICCommonClass { 62 SysBusDeviceClass parent_class; 63 64 DeviceRealize parent_realize; 65 ResettablePhases parent_phases; 66 int (*pre_save)(LoongArchPICCommonState *s); 67 int (*post_load)(LoongArchPICCommonState *s, int version_id); 68 }; 69 #endif /* HW_LOONGARCH_PIC_COMMON_H */ 70