1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU Loongson 7A1000 I/O interrupt controller. 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/bitops.h" 10 #include "qemu/log.h" 11 #include "hw/irq.h" 12 #include "hw/intc/loongarch_pch_pic.h" 13 #include "trace.h" 14 #include "qapi/error.h" 15 16 static void pch_pic_update_irq(LoongArchPICCommonState *s, uint64_t mask, 17 int level) 18 { 19 uint64_t val; 20 int irq; 21 22 if (level) { 23 val = mask & s->intirr & ~s->int_mask; 24 if (val) { 25 irq = ctz64(val); 26 s->intisr |= MAKE_64BIT_MASK(irq, 1); 27 qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 1); 28 } 29 } else { 30 /* 31 * intirr means requested pending irq 32 * do not clear pending irq for edge-triggered on lowering edge 33 */ 34 val = mask & s->intisr & ~s->intirr; 35 if (val) { 36 irq = ctz64(val); 37 s->intisr &= ~MAKE_64BIT_MASK(irq, 1); 38 qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 0); 39 } 40 } 41 } 42 43 static void pch_pic_irq_handler(void *opaque, int irq, int level) 44 { 45 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque); 46 uint64_t mask = 1ULL << irq; 47 48 assert(irq < s->irq_num); 49 trace_loongarch_pch_pic_irq_handler(irq, level); 50 51 if (s->intedge & mask) { 52 /* Edge triggered */ 53 if (level) { 54 if ((s->last_intirr & mask) == 0) { 55 /* marked pending on a rising edge */ 56 s->intirr |= mask; 57 } 58 s->last_intirr |= mask; 59 } else { 60 s->last_intirr &= ~mask; 61 } 62 } else { 63 /* Level triggered */ 64 if (level) { 65 s->intirr |= mask; 66 s->last_intirr |= mask; 67 } else { 68 s->intirr &= ~mask; 69 s->last_intirr &= ~mask; 70 } 71 } 72 pch_pic_update_irq(s, mask, level); 73 } 74 75 static uint64_t pch_pic_read(void *opaque, hwaddr addr, uint64_t field_mask) 76 { 77 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque); 78 uint64_t val = 0; 79 uint32_t offset; 80 81 offset = addr & 7; 82 addr -= offset; 83 switch (addr) { 84 case PCH_PIC_INT_ID: 85 val = s->id.data; 86 break; 87 case PCH_PIC_INT_MASK: 88 val = s->int_mask; 89 break; 90 case PCH_PIC_INT_EDGE: 91 val = s->intedge; 92 break; 93 case PCH_PIC_HTMSI_EN: 94 val = s->htmsi_en; 95 break; 96 case PCH_PIC_AUTO_CTRL0: 97 case PCH_PIC_AUTO_CTRL1: 98 /* PCH PIC connect to EXTIOI always, discard auto_ctrl access */ 99 break; 100 case PCH_PIC_INT_STATUS: 101 val = s->intisr & (~s->int_mask); 102 break; 103 case PCH_PIC_INT_POL: 104 val = s->int_polarity; 105 break; 106 case PCH_PIC_HTMSI_VEC ... PCH_PIC_HTMSI_VEC_END: 107 val = *(uint64_t *)(s->htmsi_vector + addr - PCH_PIC_HTMSI_VEC); 108 break; 109 case PCH_PIC_ROUTE_ENTRY ... PCH_PIC_ROUTE_ENTRY_END: 110 val = *(uint64_t *)(s->route_entry + addr - PCH_PIC_ROUTE_ENTRY); 111 break; 112 default: 113 qemu_log_mask(LOG_GUEST_ERROR, 114 "pch_pic_read: Bad address 0x%"PRIx64"\n", addr); 115 break; 116 } 117 118 return (val >> (offset * 8)) & field_mask; 119 } 120 121 static void pch_pic_write(void *opaque, hwaddr addr, uint64_t value, 122 uint64_t field_mask) 123 { 124 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque); 125 uint32_t offset; 126 uint64_t old, mask, data, *ptemp; 127 128 offset = addr & 7; 129 addr -= offset; 130 mask = field_mask << (offset * 8); 131 data = (value & field_mask) << (offset * 8); 132 switch (addr) { 133 case PCH_PIC_INT_MASK: 134 old = s->int_mask; 135 s->int_mask = (old & ~mask) | data; 136 if (old & ~data) { 137 pch_pic_update_irq(s, old & ~data, 1); 138 } 139 140 if (~old & data) { 141 pch_pic_update_irq(s, ~old & data, 0); 142 } 143 break; 144 case PCH_PIC_INT_EDGE: 145 s->intedge = (s->intedge & ~mask) | data; 146 break; 147 case PCH_PIC_INT_CLEAR: 148 if (s->intedge & data) { 149 s->intirr &= ~data; 150 pch_pic_update_irq(s, data, 0); 151 s->intisr &= ~data; 152 } 153 break; 154 case PCH_PIC_HTMSI_EN: 155 s->htmsi_en = (s->htmsi_en & ~mask) | data; 156 break; 157 case PCH_PIC_AUTO_CTRL0: 158 case PCH_PIC_AUTO_CTRL1: 159 /* Discard auto_ctrl access */ 160 break; 161 case PCH_PIC_INT_POL: 162 s->int_polarity = (s->int_polarity & ~mask) | data; 163 break; 164 case PCH_PIC_HTMSI_VEC ... PCH_PIC_HTMSI_VEC_END: 165 ptemp = (uint64_t *)(s->htmsi_vector + addr - PCH_PIC_HTMSI_VEC); 166 *ptemp = (*ptemp & ~mask) | data; 167 break; 168 case PCH_PIC_ROUTE_ENTRY ... PCH_PIC_ROUTE_ENTRY_END: 169 ptemp = (uint64_t *)(s->route_entry + addr - PCH_PIC_ROUTE_ENTRY); 170 *ptemp = (*ptemp & ~mask) | data; 171 break; 172 default: 173 qemu_log_mask(LOG_GUEST_ERROR, 174 "pch_pic_write: Bad address 0x%"PRIx64"\n", addr); 175 break; 176 } 177 } 178 179 static uint64_t loongarch_pch_pic_read(void *opaque, hwaddr addr, 180 unsigned size) 181 { 182 uint64_t val = 0; 183 184 switch (size) { 185 case 1: 186 val = pch_pic_read(opaque, addr, UCHAR_MAX); 187 break; 188 case 2: 189 val = pch_pic_read(opaque, addr, USHRT_MAX); 190 break; 191 case 4: 192 val = pch_pic_read(opaque, addr, UINT_MAX); 193 break; 194 case 8: 195 val = pch_pic_read(opaque, addr, UINT64_MAX); 196 break; 197 default: 198 qemu_log_mask(LOG_GUEST_ERROR, 199 "loongarch_pch_pic_read: Bad size %d\n", size); 200 break; 201 } 202 203 trace_loongarch_pch_pic_read(size, addr, val); 204 return val; 205 } 206 207 static void loongarch_pch_pic_write(void *opaque, hwaddr addr, 208 uint64_t value, unsigned size) 209 { 210 trace_loongarch_pch_pic_write(size, addr, value); 211 212 switch (size) { 213 case 1: 214 pch_pic_write(opaque, addr, value, UCHAR_MAX); 215 break; 216 case 2: 217 pch_pic_write(opaque, addr, value, USHRT_MAX); 218 break; 219 break; 220 case 4: 221 pch_pic_write(opaque, addr, value, UINT_MAX); 222 break; 223 case 8: 224 pch_pic_write(opaque, addr, value, UINT64_MAX); 225 break; 226 default: 227 qemu_log_mask(LOG_GUEST_ERROR, 228 "loongarch_pch_pic_write: Bad size %d\n", size); 229 break; 230 } 231 } 232 233 static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr, 234 unsigned size) 235 { 236 return loongarch_pch_pic_read(opaque, addr, size); 237 } 238 239 static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr, 240 uint64_t value, unsigned size) 241 { 242 loongarch_pch_pic_write(opaque, addr, value, size); 243 } 244 245 static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr, 246 unsigned size) 247 { 248 addr += PCH_PIC_INT_STATUS; 249 return loongarch_pch_pic_read(opaque, addr, size); 250 } 251 252 static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr, 253 uint64_t value, unsigned size) 254 { 255 addr += PCH_PIC_INT_STATUS; 256 loongarch_pch_pic_write(opaque, addr, value, size); 257 } 258 259 static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr, 260 unsigned size) 261 { 262 addr += PCH_PIC_ROUTE_ENTRY; 263 return loongarch_pch_pic_read(opaque, addr, size); 264 } 265 266 static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr, 267 uint64_t data, unsigned size) 268 { 269 addr += PCH_PIC_ROUTE_ENTRY; 270 loongarch_pch_pic_write(opaque, addr, data, size); 271 } 272 273 static const MemoryRegionOps loongarch_pch_pic_reg32_low_ops = { 274 .read = loongarch_pch_pic_low_readw, 275 .write = loongarch_pch_pic_low_writew, 276 .valid = { 277 .min_access_size = 4, 278 .max_access_size = 8, 279 }, 280 .impl = { 281 .min_access_size = 4, 282 .max_access_size = 4, 283 }, 284 .endianness = DEVICE_LITTLE_ENDIAN, 285 }; 286 287 static const MemoryRegionOps loongarch_pch_pic_reg32_high_ops = { 288 .read = loongarch_pch_pic_high_readw, 289 .write = loongarch_pch_pic_high_writew, 290 .valid = { 291 .min_access_size = 4, 292 .max_access_size = 8, 293 }, 294 .impl = { 295 .min_access_size = 4, 296 .max_access_size = 4, 297 }, 298 .endianness = DEVICE_LITTLE_ENDIAN, 299 }; 300 301 static const MemoryRegionOps loongarch_pch_pic_reg8_ops = { 302 .read = loongarch_pch_pic_readb, 303 .write = loongarch_pch_pic_writeb, 304 .valid = { 305 .min_access_size = 1, 306 .max_access_size = 1, 307 }, 308 .impl = { 309 .min_access_size = 1, 310 .max_access_size = 1, 311 }, 312 .endianness = DEVICE_LITTLE_ENDIAN, 313 }; 314 315 static void loongarch_pic_reset_hold(Object *obj, ResetType type) 316 { 317 LoongarchPICClass *lpc = LOONGARCH_PIC_GET_CLASS(obj); 318 319 if (lpc->parent_phases.hold) { 320 lpc->parent_phases.hold(obj, type); 321 } 322 } 323 324 static void loongarch_pic_realize(DeviceState *dev, Error **errp) 325 { 326 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev); 327 LoongarchPICClass *lpc = LOONGARCH_PIC_GET_CLASS(dev); 328 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 329 Error *local_err = NULL; 330 331 lpc->parent_realize(dev, &local_err); 332 if (local_err) { 333 error_propagate(errp, local_err); 334 return; 335 } 336 337 qdev_init_gpio_out(dev, s->parent_irq, s->irq_num); 338 qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num); 339 memory_region_init_io(&s->iomem32_low, OBJECT(dev), 340 &loongarch_pch_pic_reg32_low_ops, 341 s, PCH_PIC_NAME(.reg32_part1), 0x100); 342 memory_region_init_io(&s->iomem8, OBJECT(dev), &loongarch_pch_pic_reg8_ops, 343 s, PCH_PIC_NAME(.reg8), 0x2a0); 344 memory_region_init_io(&s->iomem32_high, OBJECT(dev), 345 &loongarch_pch_pic_reg32_high_ops, 346 s, PCH_PIC_NAME(.reg32_part2), 0xc60); 347 sysbus_init_mmio(sbd, &s->iomem32_low); 348 sysbus_init_mmio(sbd, &s->iomem8); 349 sysbus_init_mmio(sbd, &s->iomem32_high); 350 351 } 352 353 static void loongarch_pic_class_init(ObjectClass *klass, const void *data) 354 { 355 DeviceClass *dc = DEVICE_CLASS(klass); 356 LoongarchPICClass *lpc = LOONGARCH_PIC_CLASS(klass); 357 ResettableClass *rc = RESETTABLE_CLASS(klass); 358 359 resettable_class_set_parent_phases(rc, NULL, loongarch_pic_reset_hold, 360 NULL, &lpc->parent_phases); 361 device_class_set_parent_realize(dc, loongarch_pic_realize, 362 &lpc->parent_realize); 363 } 364 365 static const TypeInfo loongarch_pic_types[] = { 366 { 367 .name = TYPE_LOONGARCH_PIC, 368 .parent = TYPE_LOONGARCH_PIC_COMMON, 369 .instance_size = sizeof(LoongarchPICState), 370 .class_size = sizeof(LoongarchPICClass), 371 .class_init = loongarch_pic_class_init, 372 } 373 }; 374 375 DEFINE_TYPES(loongarch_pic_types) 376