1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU Loongson 7A1000 I/O interrupt controller. 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qemu/bitops.h" 10 #include "qemu/log.h" 11 #include "hw/irq.h" 12 #include "hw/intc/loongarch_pch_pic.h" 13 #include "trace.h" 14 #include "qapi/error.h" 15 16 static void pch_pic_update_irq(LoongArchPICCommonState *s, uint64_t mask, 17 int level) 18 { 19 uint64_t val; 20 int irq; 21 22 if (level) { 23 val = mask & s->intirr & ~s->int_mask; 24 if (val) { 25 irq = ctz64(val); 26 s->intisr |= MAKE_64BIT_MASK(irq, 1); 27 qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 1); 28 } 29 } else { 30 /* 31 * intirr means requested pending irq 32 * do not clear pending irq for edge-triggered on lowering edge 33 */ 34 val = mask & s->intisr & ~s->intirr; 35 if (val) { 36 irq = ctz64(val); 37 s->intisr &= ~MAKE_64BIT_MASK(irq, 1); 38 qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 0); 39 } 40 } 41 } 42 43 static void pch_pic_irq_handler(void *opaque, int irq, int level) 44 { 45 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque); 46 uint64_t mask = 1ULL << irq; 47 48 assert(irq < s->irq_num); 49 trace_loongarch_pch_pic_irq_handler(irq, level); 50 51 if (s->intedge & mask) { 52 /* Edge triggered */ 53 if (level) { 54 if ((s->last_intirr & mask) == 0) { 55 /* marked pending on a rising edge */ 56 s->intirr |= mask; 57 } 58 s->last_intirr |= mask; 59 } else { 60 s->last_intirr &= ~mask; 61 } 62 } else { 63 /* Level triggered */ 64 if (level) { 65 s->intirr |= mask; 66 s->last_intirr |= mask; 67 } else { 68 s->intirr &= ~mask; 69 s->last_intirr &= ~mask; 70 } 71 } 72 pch_pic_update_irq(s, mask, level); 73 } 74 75 static uint64_t pch_pic_read(void *opaque, hwaddr addr, uint64_t field_mask) 76 { 77 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque); 78 uint64_t val = 0; 79 uint32_t offset; 80 81 offset = addr & 7; 82 addr -= offset; 83 switch (addr) { 84 case PCH_PIC_INT_ID: 85 val = s->id.data; 86 break; 87 case PCH_PIC_INT_MASK: 88 val = s->int_mask; 89 break; 90 case PCH_PIC_INT_EDGE: 91 val = s->intedge; 92 break; 93 case PCH_PIC_HTMSI_EN: 94 val = s->htmsi_en; 95 break; 96 case PCH_PIC_AUTO_CTRL0: 97 case PCH_PIC_AUTO_CTRL1: 98 /* PCH PIC connect to EXTIOI always, discard auto_ctrl access */ 99 break; 100 case PCH_PIC_INT_STATUS: 101 val = s->intisr & (~s->int_mask); 102 break; 103 case PCH_PIC_INT_POL: 104 val = s->int_polarity; 105 break; 106 case PCH_PIC_HTMSI_VEC ... PCH_PIC_HTMSI_VEC_END: 107 val = *(uint64_t *)(s->htmsi_vector + addr - PCH_PIC_HTMSI_VEC); 108 break; 109 case PCH_PIC_ROUTE_ENTRY ... PCH_PIC_ROUTE_ENTRY_END: 110 val = *(uint64_t *)(s->route_entry + addr - PCH_PIC_ROUTE_ENTRY); 111 break; 112 default: 113 qemu_log_mask(LOG_GUEST_ERROR, 114 "pch_pic_read: Bad address 0x%"PRIx64"\n", addr); 115 break; 116 } 117 118 return (val >> (offset * 8)) & field_mask; 119 } 120 121 static uint64_t loongarch_pch_pic_read(void *opaque, hwaddr addr, 122 unsigned size) 123 { 124 uint64_t val = 0; 125 126 switch (size) { 127 case 1: 128 val = pch_pic_read(opaque, addr, UCHAR_MAX); 129 break; 130 case 2: 131 val = pch_pic_read(opaque, addr, USHRT_MAX); 132 break; 133 case 4: 134 val = pch_pic_read(opaque, addr, UINT_MAX); 135 break; 136 case 8: 137 val = pch_pic_read(opaque, addr, UINT64_MAX); 138 break; 139 default: 140 qemu_log_mask(LOG_GUEST_ERROR, 141 "loongarch_pch_pic_read: Bad size %d\n", size); 142 break; 143 } 144 145 return val; 146 } 147 148 static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr, 149 unsigned size) 150 { 151 uint64_t val; 152 153 val = loongarch_pch_pic_read(opaque, addr, size); 154 trace_loongarch_pch_pic_low_readw(size, addr, val); 155 return val; 156 } 157 158 static uint64_t get_writew_val(uint64_t value, uint32_t target, bool hi) 159 { 160 uint64_t mask = 0xffffffff00000000; 161 uint64_t data = target; 162 163 return hi ? (value & ~mask) | (data << 32) : (value & mask) | data; 164 } 165 166 static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr, 167 uint64_t value, unsigned size) 168 { 169 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque); 170 uint32_t old_valid, data = (uint32_t)value; 171 uint64_t old, int_mask; 172 173 trace_loongarch_pch_pic_low_writew(size, addr, data); 174 175 switch (addr) { 176 case PCH_PIC_INT_MASK: 177 old = s->int_mask; 178 s->int_mask = get_writew_val(old, data, 0); 179 old_valid = (uint32_t)old; 180 if (old_valid & ~data) { 181 pch_pic_update_irq(s, (old_valid & ~data), 1); 182 } 183 if (~old_valid & data) { 184 pch_pic_update_irq(s, (~old_valid & data), 0); 185 } 186 break; 187 case PCH_PIC_INT_MASK + 4: 188 old = s->int_mask; 189 s->int_mask = get_writew_val(old, data, 1); 190 old_valid = (uint32_t)(old >> 32); 191 int_mask = old_valid & ~data; 192 if (int_mask) { 193 pch_pic_update_irq(s, int_mask << 32, 1); 194 } 195 int_mask = ~old_valid & data; 196 if (int_mask) { 197 pch_pic_update_irq(s, int_mask << 32, 0); 198 } 199 break; 200 case PCH_PIC_INT_EDGE: 201 s->intedge = get_writew_val(s->intedge, data, 0); 202 break; 203 case PCH_PIC_INT_EDGE + 4: 204 s->intedge = get_writew_val(s->intedge, data, 1); 205 break; 206 case PCH_PIC_INT_CLEAR: 207 if (s->intedge & data) { 208 s->intirr &= (~data); 209 pch_pic_update_irq(s, data, 0); 210 s->intisr &= (~data); 211 } 212 break; 213 case PCH_PIC_INT_CLEAR + 4: 214 value <<= 32; 215 if (s->intedge & value) { 216 s->intirr &= (~value); 217 pch_pic_update_irq(s, value, 0); 218 s->intisr &= (~value); 219 } 220 break; 221 case PCH_PIC_HTMSI_EN: 222 s->htmsi_en = get_writew_val(s->htmsi_en, data, 0); 223 break; 224 case PCH_PIC_HTMSI_EN + 4: 225 s->htmsi_en = get_writew_val(s->htmsi_en, data, 1); 226 break; 227 case PCH_PIC_AUTO_CTRL0: 228 case PCH_PIC_AUTO_CTRL0 + 4: 229 case PCH_PIC_AUTO_CTRL1: 230 case PCH_PIC_AUTO_CTRL1 + 4: 231 /* discard auto_ctrl access */ 232 break; 233 default: 234 break; 235 } 236 } 237 238 static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr, 239 unsigned size) 240 { 241 uint64_t val; 242 243 addr += PCH_PIC_INT_STATUS; 244 val = loongarch_pch_pic_read(opaque, addr, size); 245 trace_loongarch_pch_pic_high_readw(size, addr, val); 246 return val; 247 } 248 249 static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr, 250 uint64_t value, unsigned size) 251 { 252 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque); 253 uint32_t data = (uint32_t)value; 254 255 addr += PCH_PIC_INT_STATUS; 256 trace_loongarch_pch_pic_high_writew(size, addr, data); 257 258 switch (addr) { 259 case PCH_PIC_INT_POL: 260 s->int_polarity = get_writew_val(s->int_polarity, data, 0); 261 break; 262 case PCH_PIC_INT_POL + 4: 263 s->int_polarity = get_writew_val(s->int_polarity, data, 1); 264 break; 265 default: 266 break; 267 } 268 } 269 270 static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr, 271 unsigned size) 272 { 273 uint64_t val; 274 275 addr += PCH_PIC_ROUTE_ENTRY; 276 val = loongarch_pch_pic_read(opaque, addr, size); 277 trace_loongarch_pch_pic_readb(size, addr, val); 278 return val; 279 } 280 281 static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr, 282 uint64_t data, unsigned size) 283 { 284 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque); 285 int32_t offset_tmp; 286 287 addr += PCH_PIC_ROUTE_ENTRY; 288 trace_loongarch_pch_pic_writeb(size, addr, data); 289 290 switch (addr) { 291 case PCH_PIC_HTMSI_VEC ... PCH_PIC_HTMSI_VEC_END: 292 offset_tmp = addr - PCH_PIC_HTMSI_VEC; 293 if (offset_tmp >= 0 && offset_tmp < 64) { 294 s->htmsi_vector[offset_tmp] = (uint8_t)(data & 0xff); 295 } 296 break; 297 case PCH_PIC_ROUTE_ENTRY ... PCH_PIC_ROUTE_ENTRY_END: 298 offset_tmp = addr - PCH_PIC_ROUTE_ENTRY; 299 if (offset_tmp >= 0 && offset_tmp < 64) { 300 s->route_entry[offset_tmp] = (uint8_t)(data & 0xff); 301 } 302 break; 303 default: 304 break; 305 } 306 } 307 308 static const MemoryRegionOps loongarch_pch_pic_reg32_low_ops = { 309 .read = loongarch_pch_pic_low_readw, 310 .write = loongarch_pch_pic_low_writew, 311 .valid = { 312 .min_access_size = 4, 313 .max_access_size = 8, 314 }, 315 .impl = { 316 .min_access_size = 4, 317 .max_access_size = 4, 318 }, 319 .endianness = DEVICE_LITTLE_ENDIAN, 320 }; 321 322 static const MemoryRegionOps loongarch_pch_pic_reg32_high_ops = { 323 .read = loongarch_pch_pic_high_readw, 324 .write = loongarch_pch_pic_high_writew, 325 .valid = { 326 .min_access_size = 4, 327 .max_access_size = 8, 328 }, 329 .impl = { 330 .min_access_size = 4, 331 .max_access_size = 4, 332 }, 333 .endianness = DEVICE_LITTLE_ENDIAN, 334 }; 335 336 static const MemoryRegionOps loongarch_pch_pic_reg8_ops = { 337 .read = loongarch_pch_pic_readb, 338 .write = loongarch_pch_pic_writeb, 339 .valid = { 340 .min_access_size = 1, 341 .max_access_size = 1, 342 }, 343 .impl = { 344 .min_access_size = 1, 345 .max_access_size = 1, 346 }, 347 .endianness = DEVICE_LITTLE_ENDIAN, 348 }; 349 350 static void loongarch_pic_reset_hold(Object *obj, ResetType type) 351 { 352 LoongarchPICClass *lpc = LOONGARCH_PIC_GET_CLASS(obj); 353 354 if (lpc->parent_phases.hold) { 355 lpc->parent_phases.hold(obj, type); 356 } 357 } 358 359 static void loongarch_pic_realize(DeviceState *dev, Error **errp) 360 { 361 LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev); 362 LoongarchPICClass *lpc = LOONGARCH_PIC_GET_CLASS(dev); 363 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 364 Error *local_err = NULL; 365 366 lpc->parent_realize(dev, &local_err); 367 if (local_err) { 368 error_propagate(errp, local_err); 369 return; 370 } 371 372 qdev_init_gpio_out(dev, s->parent_irq, s->irq_num); 373 qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num); 374 memory_region_init_io(&s->iomem32_low, OBJECT(dev), 375 &loongarch_pch_pic_reg32_low_ops, 376 s, PCH_PIC_NAME(.reg32_part1), 0x100); 377 memory_region_init_io(&s->iomem8, OBJECT(dev), &loongarch_pch_pic_reg8_ops, 378 s, PCH_PIC_NAME(.reg8), 0x2a0); 379 memory_region_init_io(&s->iomem32_high, OBJECT(dev), 380 &loongarch_pch_pic_reg32_high_ops, 381 s, PCH_PIC_NAME(.reg32_part2), 0xc60); 382 sysbus_init_mmio(sbd, &s->iomem32_low); 383 sysbus_init_mmio(sbd, &s->iomem8); 384 sysbus_init_mmio(sbd, &s->iomem32_high); 385 386 } 387 388 static void loongarch_pic_class_init(ObjectClass *klass, const void *data) 389 { 390 DeviceClass *dc = DEVICE_CLASS(klass); 391 LoongarchPICClass *lpc = LOONGARCH_PIC_CLASS(klass); 392 ResettableClass *rc = RESETTABLE_CLASS(klass); 393 394 resettable_class_set_parent_phases(rc, NULL, loongarch_pic_reset_hold, 395 NULL, &lpc->parent_phases); 396 device_class_set_parent_realize(dc, loongarch_pic_realize, 397 &lpc->parent_realize); 398 } 399 400 static const TypeInfo loongarch_pic_types[] = { 401 { 402 .name = TYPE_LOONGARCH_PIC, 403 .parent = TYPE_LOONGARCH_PIC_COMMON, 404 .instance_size = sizeof(LoongarchPICState), 405 .class_size = sizeof(LoongarchPICClass), 406 .class_init = loongarch_pic_class_init, 407 } 408 }; 409 410 DEFINE_TYPES(loongarch_pic_types) 411