arm64: dts: uniphier: fix W=2 build warnings

Fix warnings like follows:

Warning (node_name_chars_strict): Character '_' not recommended in ...

Commit 8654cb8d0371 ("dtc: up

arm64: dts: uniphier: fix W=2 build warnings

Fix warnings like follows:

Warning (node_name_chars_strict): Character '_' not recommended in ...

Commit 8654cb8d0371 ("dtc: update warning settings for new bus and
node/property name checks") says these checks are a bit subjective,
but Rob also says to not add new W=2 warnings.

The exising warnings should be fixed in order to catch new ones
easily.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: add efuse node for LD11, LD20, and PXs3

Add efuse node for UniPhier LD11, LD20, and PXs3.
This efuse node is included in soc-glue.

Signed-off-by: Keiji Hay

arm64: dts: uniphier: add efuse node for LD11, LD20, and PXs3

Add efuse node for UniPhier LD11, LD20, and PXs3.
This efuse node is included in soc-glue.

Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: add nodes of thermal monitor and thermal zone for LD20

Add nodes of thermal monitor and thermal zone for UniPhier LD20 SoC.
The thermal monitor node is included in

arm64: dts: uniphier: add nodes of thermal monitor and thermal zone for LD20

Add nodes of thermal monitor and thermal zone for UniPhier LD20 SoC.
The thermal monitor node is included in sysctrl. Since the efuse might not
have a calibrated value of thermal monitor, this patch gives the default
value for LD20.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: fix size of sdctrl node

All registers are located within 0x400 size from the base address.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

arm64: dts: uniphier: add AIDET nodes

Add UniPhier AIDET (ARM Interrupt Detector) nodes to support
active low interrupts.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socione

arm64: dts: uniphier: add AIDET nodes

Add UniPhier AIDET (ARM Interrupt Detector) nodes to support
active low interrupts.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: add reset controller node of analog amplifier

This patch adds reset controller node of analog signal amplifier
core (ADAMV) for UniPhier LD11/LD20 SoCs.

Si

arm64: dts: uniphier: add reset controller node of analog amplifier

This patch adds reset controller node of analog signal amplifier
core (ADAMV) for UniPhier LD11/LD20 SoCs.

Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: add Denali NAND controller nodes

Add NAND controller node to LD11 and LD20. Neither of them supports
the CS1 line, so pinctrl is set up for a single CS line.

arm64: dts: uniphier: add Denali NAND controller nodes

Add NAND controller node to LD11 and LD20. Neither of them supports
the CS1 line, so pinctrl is set up for a single CS line.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: use #include instead of /include/

To include dt-bindings headers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

arm64: dts: uniphier: add watchdog node for LD11 and LD20

Add nodes of watchdog timer for UniPhier LD11 and LD20 SoC.
The watchdog timer is included in sysctrl.

Signed-off-by: K

arm64: dts: uniphier: add watchdog node for LD11 and LD20

Add nodes of watchdog timer for UniPhier LD11 and LD20 SoC.
The watchdog timer is included in sysctrl.

Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: use SPDX-License-Identifier

Follow the recent trend for the license description, and fix the wrongly
stated X11 to MIT.

The X11 license text [1] is explici

arm64: dts: uniphier: use SPDX-License-Identifier

Follow the recent trend for the license description, and fix the wrongly
stated X11 to MIT.

The X11 license text [1] is explicitly for the X Consortium and has a
couple of extra clauses. The MIT license text [2] is actually what the
current DT files claim.

[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: reserve more memory for LD11/LD20

Reserve enough space below the kernel base.
The assumed address map is:
80000000 - 80ffffff : for IPP
81000000 - 81fff

arm64: dts: uniphier: reserve more memory for LD11/LD20

Reserve enough space below the kernel base.
The assumed address map is:
80000000 - 80ffffff : for IPP
81000000 - 81ffffff : for ARM secure
82000000 - : for Linux

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: fix simple-bus unit address format error

Compiling the UniPhier DT files with W=1, DTC warns like follows:

Warning (simple_bus_reg): Node /soc/smpctrl@59800000

arm64: dts: uniphier: fix simple-bus unit address format error

Compiling the UniPhier DT files with W=1, DTC warns like follows:

Warning (simple_bus_reg): Node /soc/smpctrl@59800000 simple-bus unit address format error, expected "59801000"

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: Use - instead of @ for DT OPP entries

Compiling the DT file with W=1, DTC warns like follows:

Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 ha

arm64: dts: uniphier: Use - instead of @ for DT OPP entries

Compiling the DT file with W=1, DTC warns like follows:

Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property

Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.

Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: add cdns, phy-dll-delay-sdclk(-hsmmc) for eMMC

Adjust the PHY parameters for more stable access to the eMMC device.
Set the SDCLK output delay value to 21 (includin

arm64: dts: uniphier: add cdns, phy-dll-delay-sdclk(-hsmmc) for eMMC

Adjust the PHY parameters for more stable access to the eMMC device.
Set the SDCLK output delay value to 21 (including HS200/400 modes).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: add input-delay properties to Cadence eMMC node

Since commit a89c472d8b55 ("mmc: sdhci-cadence: Update PHY delay
configuration"), PHY parameters must be specified b

arm64: dts: uniphier: add input-delay properties to Cadence eMMC node

Since commit a89c472d8b55 ("mmc: sdhci-cadence: Update PHY delay
configuration"), PHY parameters must be specified by DT.

The hard-coded settings have been converted as follows:
- SDHCI_CDNS_PHY_DLY_SD_DEFAULT -> cdns,phy-input-delay-legacy
- SDHCI_CDNS_PHY_DLY_EMMC_SDR -> cdns,phy-input-delay-mmc-highspeed
- SDHCI_CDNS_PHY_DLY_EMMC_DDR -> cdns,phy-input-delay-mmc-ddr

The following have not been moved:
- SDHCI_CDNS_PHY_DLY_SD_HS
this is unneeded in the eMMC configuration
- SDHCI_CDNS_PHY_DLY_EMMC_LEGACY
this is never enabled by the driver as it is covered by
SDHCI_CDNS_PHY_DLY_SD_DEFAULT

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: add pinctrl property to eMMC node for LD11/LD20

Now everything is ready to enable this pinctrl.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

arm64: dts: uniphier: fix no unit name warnings

Fix warnings reported when built with W=1:
Node /memory has a reg or ranges property, but no unit name

Signed-off-by: Masahiro

arm64: dts: uniphier: fix no unit name warnings

Fix warnings reported when built with W=1:
Node /memory has a reg or ranges property, but no unit name

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: add eMMC controller node for LD11/LD20

Add Cadence's eMMC controller node for LD11/LD20.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

arm64: dts: uniphier: make compatible of syscon nodes SoC-specific

These hardware blocks are SoC-specific, so their compatible strings
should be SoC-specific as well. This change has no

arm64: dts: uniphier: make compatible of syscon nodes SoC-specific

These hardware blocks are SoC-specific, so their compatible strings
should be SoC-specific as well. This change has no impact on the
actual behavior since it is controlled by the generic "simple-mfd",
"syscon" compatible strings.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC

Add a CPU clock to every CPU node and CPU OPP tables to use the
generic cpufreq driver. All the CPUs in each cluster sha

arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC

Add a CPU clock to every CPU node and CPU OPP tables to use the
generic cpufreq driver. All the CPUs in each cluster share the
same OPP table.

Note:
clock-latency-ns (300ns) was calculated based on the CPU-gear switch
sequencer spec; it takes 12 clock cycles on the sequencer running
at 50 MHz, plus a bit additional latency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

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arm64: dts: uniphier: increase register region size of sysctrl node

The System Control node has 0x10000 byte of registers. The current
reg size must be expanded to use the cpufreq drive

arm64: dts: uniphier: increase register region size of sysctrl node

The System Control node has 0x10000 byte of registers. The current
reg size must be expanded to use the cpufreq driver because the
registers controlling CPU frequency are located at offset 0x8000.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: switch over to PSCI enable method

At the first system bring-up, I chose to use spin-table because ARM
Trusted Firmware was not ready for this platform at that momen

arm64: dts: uniphier: switch over to PSCI enable method

At the first system bring-up, I chose to use spin-table because ARM
Trusted Firmware was not ready for this platform at that moment.

Actually, these SoCs are equipped with EL3 and able to provide PSCI.
Now I finished porting the ATF BL31 for the UniPhier platform, so it
is ready to migrate to PSCI enable method.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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arm64: dts: uniphier: change MIO node to SD control node

I made a mistake bacuse the Media I/O block is not implemented in
this SoC.

Signed-off-by: Masahiro Yamada <yamada.masah

arm64: dts: uniphier: change MIO node to SD control node

I made a mistake bacuse the Media I/O block is not implemented in
this SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Merge branch 'dt/irq-fix' into next/dt64

* dt/irq-fix:
arm64: dts: Fix broken architected timer interrupt trigger

This resolves a non-obvious conflict between a bugfix from

Merge branch 'dt/irq-fix' into next/dt64

* dt/irq-fix:
arm64: dts: Fix broken architected timer interrupt trigger

This resolves a non-obvious conflict between a bugfix from
v4.8 and a cleanup for the exynos7 platform.

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arm64: dts: uniphier: add specific compatible to SoC-Glue node

This is a simple MFD, but add a specific compatible just in case.

Signed-off-by: Masahiro Yamada <yamada.masahiro@soci

arm64: dts: uniphier: add specific compatible to SoC-Glue node

This is a simple MFD, but add a specific compatible just in case.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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