1/* 2 * Device Tree Source for UniPhier LD20 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * This file is dual-licensed: you can use it either under the terms 8 * of the GPL or the X11 license, at your option. Note that this dual 9 * licensing only applies to this file, and not this project as a 10 * whole. 11 * 12 * a) This file is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This file is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * Or, alternatively, 23 * 24 * b) Permission is hereby granted, free of charge, to any person 25 * obtaining a copy of this software and associated documentation 26 * files (the "Software"), to deal in the Software without 27 * restriction, including without limitation the rights to use, 28 * copy, modify, merge, publish, distribute, sublicense, and/or 29 * sell copies of the Software, and to permit persons to whom the 30 * Software is furnished to do so, subject to the following 31 * conditions: 32 * 33 * The above copyright notice and this permission notice shall be 34 * included in all copies or substantial portions of the Software. 35 * 36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 43 * OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46/memreserve/ 0x80000000 0x00080000; 47 48/ { 49 compatible = "socionext,uniphier-ld20"; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 interrupt-parent = <&gic>; 53 54 cpus { 55 #address-cells = <2>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu0>; 62 }; 63 core1 { 64 cpu = <&cpu1>; 65 }; 66 }; 67 68 cluster1 { 69 core0 { 70 cpu = <&cpu2>; 71 }; 72 core1 { 73 cpu = <&cpu3>; 74 }; 75 }; 76 }; 77 78 cpu0: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a72", "arm,armv8"; 81 reg = <0 0x000>; 82 clocks = <&sys_clk 32>; 83 enable-method = "psci"; 84 operating-points-v2 = <&cluster0_opp>; 85 }; 86 87 cpu1: cpu@1 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a72", "arm,armv8"; 90 reg = <0 0x001>; 91 clocks = <&sys_clk 32>; 92 enable-method = "psci"; 93 operating-points-v2 = <&cluster0_opp>; 94 }; 95 96 cpu2: cpu@100 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53", "arm,armv8"; 99 reg = <0 0x100>; 100 clocks = <&sys_clk 33>; 101 enable-method = "psci"; 102 operating-points-v2 = <&cluster1_opp>; 103 }; 104 105 cpu3: cpu@101 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53", "arm,armv8"; 108 reg = <0 0x101>; 109 clocks = <&sys_clk 33>; 110 enable-method = "psci"; 111 operating-points-v2 = <&cluster1_opp>; 112 }; 113 }; 114 115 cluster0_opp: opp_table0 { 116 compatible = "operating-points-v2"; 117 opp-shared; 118 119 opp@250000000 { 120 opp-hz = /bits/ 64 <250000000>; 121 clock-latency-ns = <300>; 122 }; 123 opp@275000000 { 124 opp-hz = /bits/ 64 <275000000>; 125 clock-latency-ns = <300>; 126 }; 127 opp@500000000 { 128 opp-hz = /bits/ 64 <500000000>; 129 clock-latency-ns = <300>; 130 }; 131 opp@550000000 { 132 opp-hz = /bits/ 64 <550000000>; 133 clock-latency-ns = <300>; 134 }; 135 opp@666667000 { 136 opp-hz = /bits/ 64 <666667000>; 137 clock-latency-ns = <300>; 138 }; 139 opp@733334000 { 140 opp-hz = /bits/ 64 <733334000>; 141 clock-latency-ns = <300>; 142 }; 143 opp@1000000000 { 144 opp-hz = /bits/ 64 <1000000000>; 145 clock-latency-ns = <300>; 146 }; 147 opp@1100000000 { 148 opp-hz = /bits/ 64 <1100000000>; 149 clock-latency-ns = <300>; 150 }; 151 }; 152 153 cluster1_opp: opp_table1 { 154 compatible = "operating-points-v2"; 155 opp-shared; 156 157 opp@250000000 { 158 opp-hz = /bits/ 64 <250000000>; 159 clock-latency-ns = <300>; 160 }; 161 opp@275000000 { 162 opp-hz = /bits/ 64 <275000000>; 163 clock-latency-ns = <300>; 164 }; 165 opp@500000000 { 166 opp-hz = /bits/ 64 <500000000>; 167 clock-latency-ns = <300>; 168 }; 169 opp@550000000 { 170 opp-hz = /bits/ 64 <550000000>; 171 clock-latency-ns = <300>; 172 }; 173 opp@666667000 { 174 opp-hz = /bits/ 64 <666667000>; 175 clock-latency-ns = <300>; 176 }; 177 opp@733334000 { 178 opp-hz = /bits/ 64 <733334000>; 179 clock-latency-ns = <300>; 180 }; 181 opp@1000000000 { 182 opp-hz = /bits/ 64 <1000000000>; 183 clock-latency-ns = <300>; 184 }; 185 opp@1100000000 { 186 opp-hz = /bits/ 64 <1100000000>; 187 clock-latency-ns = <300>; 188 }; 189 }; 190 191 psci { 192 compatible = "arm,psci-1.0"; 193 method = "smc"; 194 }; 195 196 clocks { 197 refclk: ref { 198 compatible = "fixed-clock"; 199 #clock-cells = <0>; 200 clock-frequency = <25000000>; 201 }; 202 }; 203 204 timer { 205 compatible = "arm,armv8-timer"; 206 interrupts = <1 13 4>, 207 <1 14 4>, 208 <1 11 4>, 209 <1 10 4>; 210 }; 211 212 soc@0 { 213 compatible = "simple-bus"; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 ranges = <0 0 0 0xffffffff>; 217 218 serial0: serial@54006800 { 219 compatible = "socionext,uniphier-uart"; 220 status = "disabled"; 221 reg = <0x54006800 0x40>; 222 interrupts = <0 33 4>; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_uart0>; 225 clocks = <&peri_clk 0>; 226 }; 227 228 serial1: serial@54006900 { 229 compatible = "socionext,uniphier-uart"; 230 status = "disabled"; 231 reg = <0x54006900 0x40>; 232 interrupts = <0 35 4>; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_uart1>; 235 clocks = <&peri_clk 1>; 236 }; 237 238 serial2: serial@54006a00 { 239 compatible = "socionext,uniphier-uart"; 240 status = "disabled"; 241 reg = <0x54006a00 0x40>; 242 interrupts = <0 37 4>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_uart2>; 245 clocks = <&peri_clk 2>; 246 }; 247 248 serial3: serial@54006b00 { 249 compatible = "socionext,uniphier-uart"; 250 status = "disabled"; 251 reg = <0x54006b00 0x40>; 252 interrupts = <0 177 4>; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_uart3>; 255 clocks = <&peri_clk 3>; 256 }; 257 258 i2c0: i2c@58780000 { 259 compatible = "socionext,uniphier-fi2c"; 260 status = "disabled"; 261 reg = <0x58780000 0x80>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 interrupts = <0 41 4>; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_i2c0>; 267 clocks = <&peri_clk 4>; 268 clock-frequency = <100000>; 269 }; 270 271 i2c1: i2c@58781000 { 272 compatible = "socionext,uniphier-fi2c"; 273 status = "disabled"; 274 reg = <0x58781000 0x80>; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 interrupts = <0 42 4>; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_i2c1>; 280 clocks = <&peri_clk 5>; 281 clock-frequency = <100000>; 282 }; 283 284 i2c2: i2c@58782000 { 285 compatible = "socionext,uniphier-fi2c"; 286 reg = <0x58782000 0x80>; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 interrupts = <0 43 4>; 290 clocks = <&peri_clk 6>; 291 clock-frequency = <400000>; 292 }; 293 294 i2c3: i2c@58783000 { 295 compatible = "socionext,uniphier-fi2c"; 296 status = "disabled"; 297 reg = <0x58783000 0x80>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 interrupts = <0 44 4>; 301 pinctrl-names = "default"; 302 pinctrl-0 = <&pinctrl_i2c3>; 303 clocks = <&peri_clk 7>; 304 clock-frequency = <100000>; 305 }; 306 307 i2c4: i2c@58784000 { 308 compatible = "socionext,uniphier-fi2c"; 309 status = "disabled"; 310 reg = <0x58784000 0x80>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 interrupts = <0 45 4>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&pinctrl_i2c4>; 316 clocks = <&peri_clk 8>; 317 clock-frequency = <100000>; 318 }; 319 320 i2c5: i2c@58785000 { 321 compatible = "socionext,uniphier-fi2c"; 322 reg = <0x58785000 0x80>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 interrupts = <0 25 4>; 326 clocks = <&peri_clk 9>; 327 clock-frequency = <400000>; 328 }; 329 330 system_bus: system-bus@58c00000 { 331 compatible = "socionext,uniphier-system-bus"; 332 status = "disabled"; 333 reg = <0x58c00000 0x400>; 334 #address-cells = <2>; 335 #size-cells = <1>; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_system_bus>; 338 }; 339 340 smpctrl@59800000 { 341 compatible = "socionext,uniphier-smpctrl"; 342 reg = <0x59801000 0x400>; 343 }; 344 345 sdctrl@59810000 { 346 compatible = "socionext,uniphier-ld20-sdctrl", 347 "simple-mfd", "syscon"; 348 reg = <0x59810000 0x800>; 349 350 sd_clk: clock { 351 compatible = "socionext,uniphier-ld20-sd-clock"; 352 #clock-cells = <1>; 353 }; 354 355 sd_rst: reset { 356 compatible = "socionext,uniphier-ld20-sd-reset"; 357 #reset-cells = <1>; 358 }; 359 }; 360 361 perictrl@59820000 { 362 compatible = "socionext,uniphier-ld20-perictrl", 363 "simple-mfd", "syscon"; 364 reg = <0x59820000 0x200>; 365 366 peri_clk: clock { 367 compatible = "socionext,uniphier-ld20-peri-clock"; 368 #clock-cells = <1>; 369 }; 370 371 peri_rst: reset { 372 compatible = "socionext,uniphier-ld20-peri-reset"; 373 #reset-cells = <1>; 374 }; 375 }; 376 377 emmc: sdhc@5a000000 { 378 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 379 reg = <0x5a000000 0x400>; 380 interrupts = <0 78 4>; 381 pinctrl-names = "default"; 382 pinctrl-0 = <&pinctrl_emmc>; 383 clocks = <&sys_clk 4>; 384 bus-width = <8>; 385 mmc-ddr-1_8v; 386 mmc-hs200-1_8v; 387 cdns,phy-input-delay-legacy = <4>; 388 cdns,phy-input-delay-mmc-highspeed = <2>; 389 cdns,phy-input-delay-mmc-ddr = <3>; 390 }; 391 392 soc-glue@5f800000 { 393 compatible = "socionext,uniphier-ld20-soc-glue", 394 "simple-mfd", "syscon"; 395 reg = <0x5f800000 0x2000>; 396 397 pinctrl: pinctrl { 398 compatible = "socionext,uniphier-ld20-pinctrl"; 399 }; 400 }; 401 402 gic: interrupt-controller@5fe00000 { 403 compatible = "arm,gic-v3"; 404 reg = <0x5fe00000 0x10000>, /* GICD */ 405 <0x5fe80000 0x80000>; /* GICR */ 406 interrupt-controller; 407 #interrupt-cells = <3>; 408 interrupts = <1 9 4>; 409 }; 410 411 sysctrl@61840000 { 412 compatible = "socionext,uniphier-ld20-sysctrl", 413 "simple-mfd", "syscon"; 414 reg = <0x61840000 0x10000>; 415 416 sys_clk: clock { 417 compatible = "socionext,uniphier-ld20-clock"; 418 #clock-cells = <1>; 419 }; 420 421 sys_rst: reset { 422 compatible = "socionext,uniphier-ld20-reset"; 423 #reset-cells = <1>; 424 }; 425 }; 426 }; 427}; 428 429/include/ "uniphier-pinctrl.dtsi" 430