1/* 2 * Device Tree Source for UniPhier LD20 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * This file is dual-licensed: you can use it either under the terms 8 * of the GPL or the X11 license, at your option. Note that this dual 9 * licensing only applies to this file, and not this project as a 10 * whole. 11 * 12 * a) This file is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This file is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * Or, alternatively, 23 * 24 * b) Permission is hereby granted, free of charge, to any person 25 * obtaining a copy of this software and associated documentation 26 * files (the "Software"), to deal in the Software without 27 * restriction, including without limitation the rights to use, 28 * copy, modify, merge, publish, distribute, sublicense, and/or 29 * sell copies of the Software, and to permit persons to whom the 30 * Software is furnished to do so, subject to the following 31 * conditions: 32 * 33 * The above copyright notice and this permission notice shall be 34 * included in all copies or substantial portions of the Software. 35 * 36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 43 * OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46/memreserve/ 0x80000000 0x00080000; 47 48/ { 49 compatible = "socionext,uniphier-ld20"; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 interrupt-parent = <&gic>; 53 54 cpus { 55 #address-cells = <2>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu0>; 62 }; 63 core1 { 64 cpu = <&cpu1>; 65 }; 66 }; 67 68 cluster1 { 69 core0 { 70 cpu = <&cpu2>; 71 }; 72 core1 { 73 cpu = <&cpu3>; 74 }; 75 }; 76 }; 77 78 cpu0: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a72", "arm,armv8"; 81 reg = <0 0x000>; 82 enable-method = "psci"; 83 }; 84 85 cpu1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a72", "arm,armv8"; 88 reg = <0 0x001>; 89 enable-method = "psci"; 90 }; 91 92 cpu2: cpu@100 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53", "arm,armv8"; 95 reg = <0 0x100>; 96 enable-method = "psci"; 97 }; 98 99 cpu3: cpu@101 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53", "arm,armv8"; 102 reg = <0 0x101>; 103 enable-method = "psci"; 104 }; 105 }; 106 107 psci { 108 compatible = "arm,psci-1.0"; 109 method = "smc"; 110 }; 111 112 clocks { 113 refclk: ref { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 clock-frequency = <25000000>; 117 }; 118 }; 119 120 timer { 121 compatible = "arm,armv8-timer"; 122 interrupts = <1 13 4>, 123 <1 14 4>, 124 <1 11 4>, 125 <1 10 4>; 126 }; 127 128 soc { 129 compatible = "simple-bus"; 130 #address-cells = <1>; 131 #size-cells = <1>; 132 ranges = <0 0 0 0xffffffff>; 133 134 serial0: serial@54006800 { 135 compatible = "socionext,uniphier-uart"; 136 status = "disabled"; 137 reg = <0x54006800 0x40>; 138 interrupts = <0 33 4>; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_uart0>; 141 clocks = <&peri_clk 0>; 142 }; 143 144 serial1: serial@54006900 { 145 compatible = "socionext,uniphier-uart"; 146 status = "disabled"; 147 reg = <0x54006900 0x40>; 148 interrupts = <0 35 4>; 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_uart1>; 151 clocks = <&peri_clk 1>; 152 }; 153 154 serial2: serial@54006a00 { 155 compatible = "socionext,uniphier-uart"; 156 status = "disabled"; 157 reg = <0x54006a00 0x40>; 158 interrupts = <0 37 4>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_uart2>; 161 clocks = <&peri_clk 2>; 162 }; 163 164 serial3: serial@54006b00 { 165 compatible = "socionext,uniphier-uart"; 166 status = "disabled"; 167 reg = <0x54006b00 0x40>; 168 interrupts = <0 177 4>; 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pinctrl_uart3>; 171 clocks = <&peri_clk 3>; 172 }; 173 174 i2c0: i2c@58780000 { 175 compatible = "socionext,uniphier-fi2c"; 176 status = "disabled"; 177 reg = <0x58780000 0x80>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 interrupts = <0 41 4>; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&pinctrl_i2c0>; 183 clocks = <&peri_clk 4>; 184 clock-frequency = <100000>; 185 }; 186 187 i2c1: i2c@58781000 { 188 compatible = "socionext,uniphier-fi2c"; 189 status = "disabled"; 190 reg = <0x58781000 0x80>; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 interrupts = <0 42 4>; 194 pinctrl-names = "default"; 195 pinctrl-0 = <&pinctrl_i2c1>; 196 clocks = <&peri_clk 5>; 197 clock-frequency = <100000>; 198 }; 199 200 i2c2: i2c@58782000 { 201 compatible = "socionext,uniphier-fi2c"; 202 reg = <0x58782000 0x80>; 203 #address-cells = <1>; 204 #size-cells = <0>; 205 interrupts = <0 43 4>; 206 clocks = <&peri_clk 6>; 207 clock-frequency = <400000>; 208 }; 209 210 i2c3: i2c@58783000 { 211 compatible = "socionext,uniphier-fi2c"; 212 status = "disabled"; 213 reg = <0x58783000 0x80>; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 interrupts = <0 44 4>; 217 pinctrl-names = "default"; 218 pinctrl-0 = <&pinctrl_i2c3>; 219 clocks = <&peri_clk 7>; 220 clock-frequency = <100000>; 221 }; 222 223 i2c4: i2c@58784000 { 224 compatible = "socionext,uniphier-fi2c"; 225 status = "disabled"; 226 reg = <0x58784000 0x80>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 interrupts = <0 45 4>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_i2c4>; 232 clocks = <&peri_clk 8>; 233 clock-frequency = <100000>; 234 }; 235 236 i2c5: i2c@58785000 { 237 compatible = "socionext,uniphier-fi2c"; 238 reg = <0x58785000 0x80>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 interrupts = <0 25 4>; 242 clocks = <&peri_clk 9>; 243 clock-frequency = <400000>; 244 }; 245 246 system_bus: system-bus@58c00000 { 247 compatible = "socionext,uniphier-system-bus"; 248 status = "disabled"; 249 reg = <0x58c00000 0x400>; 250 #address-cells = <2>; 251 #size-cells = <1>; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_system_bus>; 254 }; 255 256 smpctrl@59800000 { 257 compatible = "socionext,uniphier-smpctrl"; 258 reg = <0x59801000 0x400>; 259 }; 260 261 sdctrl@59810000 { 262 compatible = "socionext,uniphier-ld20-sdctrl", 263 "simple-mfd", "syscon"; 264 reg = <0x59810000 0x800>; 265 266 sd_clk: clock { 267 compatible = "socionext,uniphier-ld20-sd-clock"; 268 #clock-cells = <1>; 269 }; 270 271 sd_rst: reset { 272 compatible = "socionext,uniphier-ld20-sd-reset"; 273 #reset-cells = <1>; 274 }; 275 }; 276 277 perictrl@59820000 { 278 compatible = "socionext,uniphier-perictrl", 279 "simple-mfd", "syscon"; 280 reg = <0x59820000 0x200>; 281 282 peri_clk: clock { 283 compatible = "socionext,uniphier-ld20-peri-clock"; 284 #clock-cells = <1>; 285 }; 286 287 peri_rst: reset { 288 compatible = "socionext,uniphier-ld20-peri-reset"; 289 #reset-cells = <1>; 290 }; 291 }; 292 293 soc-glue@5f800000 { 294 compatible = "socionext,uniphier-soc-glue", 295 "simple-mfd", "syscon"; 296 reg = <0x5f800000 0x2000>; 297 298 pinctrl: pinctrl { 299 compatible = "socionext,uniphier-ld20-pinctrl"; 300 }; 301 }; 302 303 gic: interrupt-controller@5fe00000 { 304 compatible = "arm,gic-v3"; 305 reg = <0x5fe00000 0x10000>, /* GICD */ 306 <0x5fe80000 0x80000>; /* GICR */ 307 interrupt-controller; 308 #interrupt-cells = <3>; 309 interrupts = <1 9 4>; 310 }; 311 312 sysctrl@61840000 { 313 compatible = "socionext,uniphier-sysctrl", 314 "simple-mfd", "syscon"; 315 reg = <0x61840000 0x4000>; 316 317 sys_clk: clock { 318 compatible = "socionext,uniphier-ld20-clock"; 319 #clock-cells = <1>; 320 }; 321 322 sys_rst: reset { 323 compatible = "socionext,uniphier-ld20-reset"; 324 #reset-cells = <1>; 325 }; 326 }; 327 }; 328}; 329 330/include/ "uniphier-pinctrl.dtsi" 331