1/*
2 * Device Tree Source for UniPhier LD20 SoC
3 *
4 * Copyright (C) 2015-2016 Socionext Inc.
5 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */
9
10#include <dt-bindings/thermal/thermal.h>
11
12/memreserve/ 0x80000000 0x02000000;
13
14/ {
15	compatible = "socionext,uniphier-ld20";
16	#address-cells = <2>;
17	#size-cells = <2>;
18	interrupt-parent = <&gic>;
19
20	cpus {
21		#address-cells = <2>;
22		#size-cells = <0>;
23
24		cpu-map {
25			cluster0 {
26				core0 {
27					cpu = <&cpu0>;
28				};
29				core1 {
30					cpu = <&cpu1>;
31				};
32			};
33
34			cluster1 {
35				core0 {
36					cpu = <&cpu2>;
37				};
38				core1 {
39					cpu = <&cpu3>;
40				};
41			};
42		};
43
44		cpu0: cpu@0 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a72", "arm,armv8";
47			reg = <0 0x000>;
48			clocks = <&sys_clk 32>;
49			enable-method = "psci";
50			operating-points-v2 = <&cluster0_opp>;
51			#cooling-cells = <2>;
52		};
53
54		cpu1: cpu@1 {
55			device_type = "cpu";
56			compatible = "arm,cortex-a72", "arm,armv8";
57			reg = <0 0x001>;
58			clocks = <&sys_clk 32>;
59			enable-method = "psci";
60			operating-points-v2 = <&cluster0_opp>;
61		};
62
63		cpu2: cpu@100 {
64			device_type = "cpu";
65			compatible = "arm,cortex-a53", "arm,armv8";
66			reg = <0 0x100>;
67			clocks = <&sys_clk 33>;
68			enable-method = "psci";
69			operating-points-v2 = <&cluster1_opp>;
70			#cooling-cells = <2>;
71		};
72
73		cpu3: cpu@101 {
74			device_type = "cpu";
75			compatible = "arm,cortex-a53", "arm,armv8";
76			reg = <0 0x101>;
77			clocks = <&sys_clk 33>;
78			enable-method = "psci";
79			operating-points-v2 = <&cluster1_opp>;
80		};
81	};
82
83	cluster0_opp: opp_table0 {
84		compatible = "operating-points-v2";
85		opp-shared;
86
87		opp-250000000 {
88			opp-hz = /bits/ 64 <250000000>;
89			clock-latency-ns = <300>;
90		};
91		opp-275000000 {
92			opp-hz = /bits/ 64 <275000000>;
93			clock-latency-ns = <300>;
94		};
95		opp-500000000 {
96			opp-hz = /bits/ 64 <500000000>;
97			clock-latency-ns = <300>;
98		};
99		opp-550000000 {
100			opp-hz = /bits/ 64 <550000000>;
101			clock-latency-ns = <300>;
102		};
103		opp-666667000 {
104			opp-hz = /bits/ 64 <666667000>;
105			clock-latency-ns = <300>;
106		};
107		opp-733334000 {
108			opp-hz = /bits/ 64 <733334000>;
109			clock-latency-ns = <300>;
110		};
111		opp-1000000000 {
112			opp-hz = /bits/ 64 <1000000000>;
113			clock-latency-ns = <300>;
114		};
115		opp-1100000000 {
116			opp-hz = /bits/ 64 <1100000000>;
117			clock-latency-ns = <300>;
118		};
119	};
120
121	cluster1_opp: opp_table1 {
122		compatible = "operating-points-v2";
123		opp-shared;
124
125		opp-250000000 {
126			opp-hz = /bits/ 64 <250000000>;
127			clock-latency-ns = <300>;
128		};
129		opp-275000000 {
130			opp-hz = /bits/ 64 <275000000>;
131			clock-latency-ns = <300>;
132		};
133		opp-500000000 {
134			opp-hz = /bits/ 64 <500000000>;
135			clock-latency-ns = <300>;
136		};
137		opp-550000000 {
138			opp-hz = /bits/ 64 <550000000>;
139			clock-latency-ns = <300>;
140		};
141		opp-666667000 {
142			opp-hz = /bits/ 64 <666667000>;
143			clock-latency-ns = <300>;
144		};
145		opp-733334000 {
146			opp-hz = /bits/ 64 <733334000>;
147			clock-latency-ns = <300>;
148		};
149		opp-1000000000 {
150			opp-hz = /bits/ 64 <1000000000>;
151			clock-latency-ns = <300>;
152		};
153		opp-1100000000 {
154			opp-hz = /bits/ 64 <1100000000>;
155			clock-latency-ns = <300>;
156		};
157	};
158
159	psci {
160		compatible = "arm,psci-1.0";
161		method = "smc";
162	};
163
164	clocks {
165		refclk: ref {
166			compatible = "fixed-clock";
167			#clock-cells = <0>;
168			clock-frequency = <25000000>;
169		};
170	};
171
172	timer {
173		compatible = "arm,armv8-timer";
174		interrupts = <1 13 4>,
175			     <1 14 4>,
176			     <1 11 4>,
177			     <1 10 4>;
178	};
179
180	thermal-zones {
181		cpu-thermal {
182			polling-delay-passive = <250>;	/* 250ms */
183			polling-delay = <1000>;		/* 1000ms */
184			thermal-sensors = <&pvtctl>;
185
186			trips {
187				cpu_crit: cpu-crit {
188					temperature = <110000>;	/* 110C */
189					hysteresis = <2000>;
190					type = "critical";
191				};
192				cpu_alert: cpu-alert {
193					temperature = <100000>;	/* 100C */
194					hysteresis = <2000>;
195					type = "passive";
196				};
197			};
198
199			cooling-maps {
200				map0 {
201					trip = <&cpu_alert>;
202					cooling-device = <&cpu0
203					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
204				};
205				map1 {
206					trip = <&cpu_alert>;
207					cooling-device = <&cpu2
208					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
209				};
210			};
211		};
212	};
213
214	soc@0 {
215		compatible = "simple-bus";
216		#address-cells = <1>;
217		#size-cells = <1>;
218		ranges = <0 0 0 0xffffffff>;
219
220		serial0: serial@54006800 {
221			compatible = "socionext,uniphier-uart";
222			status = "disabled";
223			reg = <0x54006800 0x40>;
224			interrupts = <0 33 4>;
225			pinctrl-names = "default";
226			pinctrl-0 = <&pinctrl_uart0>;
227			clocks = <&peri_clk 0>;
228		};
229
230		serial1: serial@54006900 {
231			compatible = "socionext,uniphier-uart";
232			status = "disabled";
233			reg = <0x54006900 0x40>;
234			interrupts = <0 35 4>;
235			pinctrl-names = "default";
236			pinctrl-0 = <&pinctrl_uart1>;
237			clocks = <&peri_clk 1>;
238		};
239
240		serial2: serial@54006a00 {
241			compatible = "socionext,uniphier-uart";
242			status = "disabled";
243			reg = <0x54006a00 0x40>;
244			interrupts = <0 37 4>;
245			pinctrl-names = "default";
246			pinctrl-0 = <&pinctrl_uart2>;
247			clocks = <&peri_clk 2>;
248		};
249
250		serial3: serial@54006b00 {
251			compatible = "socionext,uniphier-uart";
252			status = "disabled";
253			reg = <0x54006b00 0x40>;
254			interrupts = <0 177 4>;
255			pinctrl-names = "default";
256			pinctrl-0 = <&pinctrl_uart3>;
257			clocks = <&peri_clk 3>;
258		};
259
260		adamv@57920000 {
261			compatible = "socionext,uniphier-ld20-adamv",
262				     "simple-mfd", "syscon";
263			reg = <0x57920000 0x1000>;
264
265			adamv_rst: reset {
266				compatible = "socionext,uniphier-ld20-adamv-reset";
267				#reset-cells = <1>;
268			};
269		};
270
271		i2c0: i2c@58780000 {
272			compatible = "socionext,uniphier-fi2c";
273			status = "disabled";
274			reg = <0x58780000 0x80>;
275			#address-cells = <1>;
276			#size-cells = <0>;
277			interrupts = <0 41 4>;
278			pinctrl-names = "default";
279			pinctrl-0 = <&pinctrl_i2c0>;
280			clocks = <&peri_clk 4>;
281			clock-frequency = <100000>;
282		};
283
284		i2c1: i2c@58781000 {
285			compatible = "socionext,uniphier-fi2c";
286			status = "disabled";
287			reg = <0x58781000 0x80>;
288			#address-cells = <1>;
289			#size-cells = <0>;
290			interrupts = <0 42 4>;
291			pinctrl-names = "default";
292			pinctrl-0 = <&pinctrl_i2c1>;
293			clocks = <&peri_clk 5>;
294			clock-frequency = <100000>;
295		};
296
297		i2c2: i2c@58782000 {
298			compatible = "socionext,uniphier-fi2c";
299			reg = <0x58782000 0x80>;
300			#address-cells = <1>;
301			#size-cells = <0>;
302			interrupts = <0 43 4>;
303			clocks = <&peri_clk 6>;
304			clock-frequency = <400000>;
305		};
306
307		i2c3: i2c@58783000 {
308			compatible = "socionext,uniphier-fi2c";
309			status = "disabled";
310			reg = <0x58783000 0x80>;
311			#address-cells = <1>;
312			#size-cells = <0>;
313			interrupts = <0 44 4>;
314			pinctrl-names = "default";
315			pinctrl-0 = <&pinctrl_i2c3>;
316			clocks = <&peri_clk 7>;
317			clock-frequency = <100000>;
318		};
319
320		i2c4: i2c@58784000 {
321			compatible = "socionext,uniphier-fi2c";
322			status = "disabled";
323			reg = <0x58784000 0x80>;
324			#address-cells = <1>;
325			#size-cells = <0>;
326			interrupts = <0 45 4>;
327			pinctrl-names = "default";
328			pinctrl-0 = <&pinctrl_i2c4>;
329			clocks = <&peri_clk 8>;
330			clock-frequency = <100000>;
331		};
332
333		i2c5: i2c@58785000 {
334			compatible = "socionext,uniphier-fi2c";
335			reg = <0x58785000 0x80>;
336			#address-cells = <1>;
337			#size-cells = <0>;
338			interrupts = <0 25 4>;
339			clocks = <&peri_clk 9>;
340			clock-frequency = <400000>;
341		};
342
343		system_bus: system-bus@58c00000 {
344			compatible = "socionext,uniphier-system-bus";
345			status = "disabled";
346			reg = <0x58c00000 0x400>;
347			#address-cells = <2>;
348			#size-cells = <1>;
349			pinctrl-names = "default";
350			pinctrl-0 = <&pinctrl_system_bus>;
351		};
352
353		smpctrl@59801000 {
354			compatible = "socionext,uniphier-smpctrl";
355			reg = <0x59801000 0x400>;
356		};
357
358		sdctrl@59810000 {
359			compatible = "socionext,uniphier-ld20-sdctrl",
360				     "simple-mfd", "syscon";
361			reg = <0x59810000 0x400>;
362
363			sd_clk: clock {
364				compatible = "socionext,uniphier-ld20-sd-clock";
365				#clock-cells = <1>;
366			};
367
368			sd_rst: reset {
369				compatible = "socionext,uniphier-ld20-sd-reset";
370				#reset-cells = <1>;
371			};
372		};
373
374		perictrl@59820000 {
375			compatible = "socionext,uniphier-ld20-perictrl",
376				     "simple-mfd", "syscon";
377			reg = <0x59820000 0x200>;
378
379			peri_clk: clock {
380				compatible = "socionext,uniphier-ld20-peri-clock";
381				#clock-cells = <1>;
382			};
383
384			peri_rst: reset {
385				compatible = "socionext,uniphier-ld20-peri-reset";
386				#reset-cells = <1>;
387			};
388		};
389
390		emmc: sdhc@5a000000 {
391			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
392			reg = <0x5a000000 0x400>;
393			interrupts = <0 78 4>;
394			pinctrl-names = "default";
395			pinctrl-0 = <&pinctrl_emmc>;
396			clocks = <&sys_clk 4>;
397			bus-width = <8>;
398			mmc-ddr-1_8v;
399			mmc-hs200-1_8v;
400			cdns,phy-input-delay-legacy = <4>;
401			cdns,phy-input-delay-mmc-highspeed = <2>;
402			cdns,phy-input-delay-mmc-ddr = <3>;
403			cdns,phy-dll-delay-sdclk = <21>;
404			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
405		};
406
407		soc-glue@5f800000 {
408			compatible = "socionext,uniphier-ld20-soc-glue",
409				     "simple-mfd", "syscon";
410			reg = <0x5f800000 0x2000>;
411
412			pinctrl: pinctrl {
413				compatible = "socionext,uniphier-ld20-pinctrl";
414			};
415		};
416
417		aidet: aidet@5fc20000 {
418			compatible = "socionext,uniphier-ld20-aidet";
419			reg = <0x5fc20000 0x200>;
420			interrupt-controller;
421			#interrupt-cells = <2>;
422		};
423
424		gic: interrupt-controller@5fe00000 {
425			compatible = "arm,gic-v3";
426			reg = <0x5fe00000 0x10000>,	/* GICD */
427			      <0x5fe80000 0x80000>;	/* GICR */
428			interrupt-controller;
429			#interrupt-cells = <3>;
430			interrupts = <1 9 4>;
431		};
432
433		sysctrl@61840000 {
434			compatible = "socionext,uniphier-ld20-sysctrl",
435				     "simple-mfd", "syscon";
436			reg = <0x61840000 0x10000>;
437
438			sys_clk: clock {
439				compatible = "socionext,uniphier-ld20-clock";
440				#clock-cells = <1>;
441			};
442
443			sys_rst: reset {
444				compatible = "socionext,uniphier-ld20-reset";
445				#reset-cells = <1>;
446			};
447
448			watchdog {
449				compatible = "socionext,uniphier-wdt";
450			};
451
452			pvtctl: pvtctl {
453				compatible = "socionext,uniphier-ld20-thermal";
454				interrupts = <0 3 4>;
455				#thermal-sensor-cells = <0>;
456				socionext,tmod-calibration = <0x0f22 0x68ee>;
457			};
458		};
459
460		nand: nand@68000000 {
461			compatible = "socionext,uniphier-denali-nand-v5b";
462			status = "disabled";
463			reg-names = "nand_data", "denali_reg";
464			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
465			interrupts = <0 65 4>;
466			pinctrl-names = "default";
467			pinctrl-0 = <&pinctrl_nand>;
468			clocks = <&sys_clk 2>;
469		};
470	};
471};
472
473#include "uniphier-pinctrl.dtsi"
474