1/* 2 * Device Tree Source for UniPhier LD20 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10/memreserve/ 0x80000000 0x02000000; 11 12/ { 13 compatible = "socionext,uniphier-ld20"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 }; 31 32 cluster1 { 33 core0 { 34 cpu = <&cpu2>; 35 }; 36 core1 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 }; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a72", "arm,armv8"; 45 reg = <0 0x000>; 46 clocks = <&sys_clk 32>; 47 enable-method = "psci"; 48 operating-points-v2 = <&cluster0_opp>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a72", "arm,armv8"; 54 reg = <0 0x001>; 55 clocks = <&sys_clk 32>; 56 enable-method = "psci"; 57 operating-points-v2 = <&cluster0_opp>; 58 }; 59 60 cpu2: cpu@100 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53", "arm,armv8"; 63 reg = <0 0x100>; 64 clocks = <&sys_clk 33>; 65 enable-method = "psci"; 66 operating-points-v2 = <&cluster1_opp>; 67 }; 68 69 cpu3: cpu@101 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <0 0x101>; 73 clocks = <&sys_clk 33>; 74 enable-method = "psci"; 75 operating-points-v2 = <&cluster1_opp>; 76 }; 77 }; 78 79 cluster0_opp: opp_table0 { 80 compatible = "operating-points-v2"; 81 opp-shared; 82 83 opp-250000000 { 84 opp-hz = /bits/ 64 <250000000>; 85 clock-latency-ns = <300>; 86 }; 87 opp-275000000 { 88 opp-hz = /bits/ 64 <275000000>; 89 clock-latency-ns = <300>; 90 }; 91 opp-500000000 { 92 opp-hz = /bits/ 64 <500000000>; 93 clock-latency-ns = <300>; 94 }; 95 opp-550000000 { 96 opp-hz = /bits/ 64 <550000000>; 97 clock-latency-ns = <300>; 98 }; 99 opp-666667000 { 100 opp-hz = /bits/ 64 <666667000>; 101 clock-latency-ns = <300>; 102 }; 103 opp-733334000 { 104 opp-hz = /bits/ 64 <733334000>; 105 clock-latency-ns = <300>; 106 }; 107 opp-1000000000 { 108 opp-hz = /bits/ 64 <1000000000>; 109 clock-latency-ns = <300>; 110 }; 111 opp-1100000000 { 112 opp-hz = /bits/ 64 <1100000000>; 113 clock-latency-ns = <300>; 114 }; 115 }; 116 117 cluster1_opp: opp_table1 { 118 compatible = "operating-points-v2"; 119 opp-shared; 120 121 opp-250000000 { 122 opp-hz = /bits/ 64 <250000000>; 123 clock-latency-ns = <300>; 124 }; 125 opp-275000000 { 126 opp-hz = /bits/ 64 <275000000>; 127 clock-latency-ns = <300>; 128 }; 129 opp-500000000 { 130 opp-hz = /bits/ 64 <500000000>; 131 clock-latency-ns = <300>; 132 }; 133 opp-550000000 { 134 opp-hz = /bits/ 64 <550000000>; 135 clock-latency-ns = <300>; 136 }; 137 opp-666667000 { 138 opp-hz = /bits/ 64 <666667000>; 139 clock-latency-ns = <300>; 140 }; 141 opp-733334000 { 142 opp-hz = /bits/ 64 <733334000>; 143 clock-latency-ns = <300>; 144 }; 145 opp-1000000000 { 146 opp-hz = /bits/ 64 <1000000000>; 147 clock-latency-ns = <300>; 148 }; 149 opp-1100000000 { 150 opp-hz = /bits/ 64 <1100000000>; 151 clock-latency-ns = <300>; 152 }; 153 }; 154 155 psci { 156 compatible = "arm,psci-1.0"; 157 method = "smc"; 158 }; 159 160 clocks { 161 refclk: ref { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <25000000>; 165 }; 166 }; 167 168 timer { 169 compatible = "arm,armv8-timer"; 170 interrupts = <1 13 4>, 171 <1 14 4>, 172 <1 11 4>, 173 <1 10 4>; 174 }; 175 176 soc@0 { 177 compatible = "simple-bus"; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 ranges = <0 0 0 0xffffffff>; 181 182 serial0: serial@54006800 { 183 compatible = "socionext,uniphier-uart"; 184 status = "disabled"; 185 reg = <0x54006800 0x40>; 186 interrupts = <0 33 4>; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&pinctrl_uart0>; 189 clocks = <&peri_clk 0>; 190 }; 191 192 serial1: serial@54006900 { 193 compatible = "socionext,uniphier-uart"; 194 status = "disabled"; 195 reg = <0x54006900 0x40>; 196 interrupts = <0 35 4>; 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_uart1>; 199 clocks = <&peri_clk 1>; 200 }; 201 202 serial2: serial@54006a00 { 203 compatible = "socionext,uniphier-uart"; 204 status = "disabled"; 205 reg = <0x54006a00 0x40>; 206 interrupts = <0 37 4>; 207 pinctrl-names = "default"; 208 pinctrl-0 = <&pinctrl_uart2>; 209 clocks = <&peri_clk 2>; 210 }; 211 212 serial3: serial@54006b00 { 213 compatible = "socionext,uniphier-uart"; 214 status = "disabled"; 215 reg = <0x54006b00 0x40>; 216 interrupts = <0 177 4>; 217 pinctrl-names = "default"; 218 pinctrl-0 = <&pinctrl_uart3>; 219 clocks = <&peri_clk 3>; 220 }; 221 222 i2c0: i2c@58780000 { 223 compatible = "socionext,uniphier-fi2c"; 224 status = "disabled"; 225 reg = <0x58780000 0x80>; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 interrupts = <0 41 4>; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_i2c0>; 231 clocks = <&peri_clk 4>; 232 clock-frequency = <100000>; 233 }; 234 235 i2c1: i2c@58781000 { 236 compatible = "socionext,uniphier-fi2c"; 237 status = "disabled"; 238 reg = <0x58781000 0x80>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 interrupts = <0 42 4>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_i2c1>; 244 clocks = <&peri_clk 5>; 245 clock-frequency = <100000>; 246 }; 247 248 i2c2: i2c@58782000 { 249 compatible = "socionext,uniphier-fi2c"; 250 reg = <0x58782000 0x80>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 interrupts = <0 43 4>; 254 clocks = <&peri_clk 6>; 255 clock-frequency = <400000>; 256 }; 257 258 i2c3: i2c@58783000 { 259 compatible = "socionext,uniphier-fi2c"; 260 status = "disabled"; 261 reg = <0x58783000 0x80>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 interrupts = <0 44 4>; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_i2c3>; 267 clocks = <&peri_clk 7>; 268 clock-frequency = <100000>; 269 }; 270 271 i2c4: i2c@58784000 { 272 compatible = "socionext,uniphier-fi2c"; 273 status = "disabled"; 274 reg = <0x58784000 0x80>; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 interrupts = <0 45 4>; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_i2c4>; 280 clocks = <&peri_clk 8>; 281 clock-frequency = <100000>; 282 }; 283 284 i2c5: i2c@58785000 { 285 compatible = "socionext,uniphier-fi2c"; 286 reg = <0x58785000 0x80>; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 interrupts = <0 25 4>; 290 clocks = <&peri_clk 9>; 291 clock-frequency = <400000>; 292 }; 293 294 system_bus: system-bus@58c00000 { 295 compatible = "socionext,uniphier-system-bus"; 296 status = "disabled"; 297 reg = <0x58c00000 0x400>; 298 #address-cells = <2>; 299 #size-cells = <1>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pinctrl_system_bus>; 302 }; 303 304 smpctrl@59801000 { 305 compatible = "socionext,uniphier-smpctrl"; 306 reg = <0x59801000 0x400>; 307 }; 308 309 sdctrl@59810000 { 310 compatible = "socionext,uniphier-ld20-sdctrl", 311 "simple-mfd", "syscon"; 312 reg = <0x59810000 0x800>; 313 314 sd_clk: clock { 315 compatible = "socionext,uniphier-ld20-sd-clock"; 316 #clock-cells = <1>; 317 }; 318 319 sd_rst: reset { 320 compatible = "socionext,uniphier-ld20-sd-reset"; 321 #reset-cells = <1>; 322 }; 323 }; 324 325 perictrl@59820000 { 326 compatible = "socionext,uniphier-ld20-perictrl", 327 "simple-mfd", "syscon"; 328 reg = <0x59820000 0x200>; 329 330 peri_clk: clock { 331 compatible = "socionext,uniphier-ld20-peri-clock"; 332 #clock-cells = <1>; 333 }; 334 335 peri_rst: reset { 336 compatible = "socionext,uniphier-ld20-peri-reset"; 337 #reset-cells = <1>; 338 }; 339 }; 340 341 emmc: sdhc@5a000000 { 342 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 343 reg = <0x5a000000 0x400>; 344 interrupts = <0 78 4>; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&pinctrl_emmc>; 347 clocks = <&sys_clk 4>; 348 bus-width = <8>; 349 mmc-ddr-1_8v; 350 mmc-hs200-1_8v; 351 cdns,phy-input-delay-legacy = <4>; 352 cdns,phy-input-delay-mmc-highspeed = <2>; 353 cdns,phy-input-delay-mmc-ddr = <3>; 354 cdns,phy-dll-delay-sdclk = <21>; 355 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 356 }; 357 358 soc-glue@5f800000 { 359 compatible = "socionext,uniphier-ld20-soc-glue", 360 "simple-mfd", "syscon"; 361 reg = <0x5f800000 0x2000>; 362 363 pinctrl: pinctrl { 364 compatible = "socionext,uniphier-ld20-pinctrl"; 365 }; 366 }; 367 368 gic: interrupt-controller@5fe00000 { 369 compatible = "arm,gic-v3"; 370 reg = <0x5fe00000 0x10000>, /* GICD */ 371 <0x5fe80000 0x80000>; /* GICR */ 372 interrupt-controller; 373 #interrupt-cells = <3>; 374 interrupts = <1 9 4>; 375 }; 376 377 sysctrl@61840000 { 378 compatible = "socionext,uniphier-ld20-sysctrl", 379 "simple-mfd", "syscon"; 380 reg = <0x61840000 0x10000>; 381 382 sys_clk: clock { 383 compatible = "socionext,uniphier-ld20-clock"; 384 #clock-cells = <1>; 385 }; 386 387 sys_rst: reset { 388 compatible = "socionext,uniphier-ld20-reset"; 389 #reset-cells = <1>; 390 }; 391 }; 392 }; 393}; 394 395/include/ "uniphier-pinctrl.dtsi" 396