1/* 2 * Device Tree Source for UniPhier LD20 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * This file is dual-licensed: you can use it either under the terms 8 * of the GPL or the X11 license, at your option. Note that this dual 9 * licensing only applies to this file, and not this project as a 10 * whole. 11 * 12 * a) This file is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This file is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * Or, alternatively, 23 * 24 * b) Permission is hereby granted, free of charge, to any person 25 * obtaining a copy of this software and associated documentation 26 * files (the "Software"), to deal in the Software without 27 * restriction, including without limitation the rights to use, 28 * copy, modify, merge, publish, distribute, sublicense, and/or 29 * sell copies of the Software, and to permit persons to whom the 30 * Software is furnished to do so, subject to the following 31 * conditions: 32 * 33 * The above copyright notice and this permission notice shall be 34 * included in all copies or substantial portions of the Software. 35 * 36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 43 * OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ 47 48/ { 49 compatible = "socionext,uniphier-ld20"; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 interrupt-parent = <&gic>; 53 54 cpus { 55 #address-cells = <2>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu0>; 62 }; 63 core1 { 64 cpu = <&cpu1>; 65 }; 66 }; 67 68 cluster1 { 69 core0 { 70 cpu = <&cpu2>; 71 }; 72 core1 { 73 cpu = <&cpu3>; 74 }; 75 }; 76 }; 77 78 cpu0: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a72", "arm,armv8"; 81 reg = <0 0x000>; 82 enable-method = "spin-table"; 83 cpu-release-addr = <0 0x80000000>; 84 }; 85 86 cpu1: cpu@1 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a72", "arm,armv8"; 89 reg = <0 0x001>; 90 enable-method = "spin-table"; 91 cpu-release-addr = <0 0x80000000>; 92 }; 93 94 cpu2: cpu@100 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53", "arm,armv8"; 97 reg = <0 0x100>; 98 enable-method = "spin-table"; 99 cpu-release-addr = <0 0x80000000>; 100 }; 101 102 cpu3: cpu@101 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a53", "arm,armv8"; 105 reg = <0 0x101>; 106 enable-method = "spin-table"; 107 cpu-release-addr = <0 0x80000000>; 108 }; 109 }; 110 111 clocks { 112 refclk: ref { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <25000000>; 116 }; 117 }; 118 119 timer { 120 compatible = "arm,armv8-timer"; 121 interrupts = <1 13 4>, 122 <1 14 4>, 123 <1 11 4>, 124 <1 10 4>; 125 }; 126 127 soc { 128 compatible = "simple-bus"; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 ranges = <0 0 0 0xffffffff>; 132 133 serial0: serial@54006800 { 134 compatible = "socionext,uniphier-uart"; 135 status = "disabled"; 136 reg = <0x54006800 0x40>; 137 interrupts = <0 33 4>; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_uart0>; 140 clocks = <&peri_clk 0>; 141 }; 142 143 serial1: serial@54006900 { 144 compatible = "socionext,uniphier-uart"; 145 status = "disabled"; 146 reg = <0x54006900 0x40>; 147 interrupts = <0 35 4>; 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pinctrl_uart1>; 150 clocks = <&peri_clk 1>; 151 }; 152 153 serial2: serial@54006a00 { 154 compatible = "socionext,uniphier-uart"; 155 status = "disabled"; 156 reg = <0x54006a00 0x40>; 157 interrupts = <0 37 4>; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_uart2>; 160 clocks = <&peri_clk 2>; 161 }; 162 163 serial3: serial@54006b00 { 164 compatible = "socionext,uniphier-uart"; 165 status = "disabled"; 166 reg = <0x54006b00 0x40>; 167 interrupts = <0 177 4>; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_uart3>; 170 clocks = <&peri_clk 3>; 171 }; 172 173 i2c0: i2c@58780000 { 174 compatible = "socionext,uniphier-fi2c"; 175 status = "disabled"; 176 reg = <0x58780000 0x80>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 interrupts = <0 41 4>; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_i2c0>; 182 clocks = <&peri_clk 4>; 183 clock-frequency = <100000>; 184 }; 185 186 i2c1: i2c@58781000 { 187 compatible = "socionext,uniphier-fi2c"; 188 status = "disabled"; 189 reg = <0x58781000 0x80>; 190 #address-cells = <1>; 191 #size-cells = <0>; 192 interrupts = <0 42 4>; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&pinctrl_i2c1>; 195 clocks = <&peri_clk 5>; 196 clock-frequency = <100000>; 197 }; 198 199 i2c2: i2c@58782000 { 200 compatible = "socionext,uniphier-fi2c"; 201 reg = <0x58782000 0x80>; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 interrupts = <0 43 4>; 205 clocks = <&peri_clk 6>; 206 clock-frequency = <400000>; 207 }; 208 209 i2c3: i2c@58783000 { 210 compatible = "socionext,uniphier-fi2c"; 211 status = "disabled"; 212 reg = <0x58783000 0x80>; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 interrupts = <0 44 4>; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_i2c3>; 218 clocks = <&peri_clk 7>; 219 clock-frequency = <100000>; 220 }; 221 222 i2c4: i2c@58784000 { 223 compatible = "socionext,uniphier-fi2c"; 224 status = "disabled"; 225 reg = <0x58784000 0x80>; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 interrupts = <0 45 4>; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_i2c4>; 231 clocks = <&peri_clk 8>; 232 clock-frequency = <100000>; 233 }; 234 235 i2c5: i2c@58785000 { 236 compatible = "socionext,uniphier-fi2c"; 237 reg = <0x58785000 0x80>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 interrupts = <0 25 4>; 241 clocks = <&peri_clk 9>; 242 clock-frequency = <400000>; 243 }; 244 245 system_bus: system-bus@58c00000 { 246 compatible = "socionext,uniphier-system-bus"; 247 status = "disabled"; 248 reg = <0x58c00000 0x400>; 249 #address-cells = <2>; 250 #size-cells = <1>; 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_system_bus>; 253 }; 254 255 smpctrl@59800000 { 256 compatible = "socionext,uniphier-smpctrl"; 257 reg = <0x59801000 0x400>; 258 }; 259 260 sdctrl@59810000 { 261 compatible = "socionext,uniphier-ld20-sdctrl", 262 "simple-mfd", "syscon"; 263 reg = <0x59810000 0x800>; 264 265 sd_clk: clock { 266 compatible = "socionext,uniphier-ld20-sd-clock"; 267 #clock-cells = <1>; 268 }; 269 270 sd_rst: reset { 271 compatible = "socionext,uniphier-ld20-sd-reset"; 272 #reset-cells = <1>; 273 }; 274 }; 275 276 perictrl@59820000 { 277 compatible = "socionext,uniphier-perictrl", 278 "simple-mfd", "syscon"; 279 reg = <0x59820000 0x200>; 280 281 peri_clk: clock { 282 compatible = "socionext,uniphier-ld20-peri-clock"; 283 #clock-cells = <1>; 284 }; 285 286 peri_rst: reset { 287 compatible = "socionext,uniphier-ld20-peri-reset"; 288 #reset-cells = <1>; 289 }; 290 }; 291 292 soc-glue@5f800000 { 293 compatible = "socionext,uniphier-soc-glue", 294 "simple-mfd", "syscon"; 295 reg = <0x5f800000 0x2000>; 296 297 pinctrl: pinctrl { 298 compatible = "socionext,uniphier-ld20-pinctrl"; 299 }; 300 }; 301 302 gic: interrupt-controller@5fe00000 { 303 compatible = "arm,gic-v3"; 304 reg = <0x5fe00000 0x10000>, /* GICD */ 305 <0x5fe80000 0x80000>; /* GICR */ 306 interrupt-controller; 307 #interrupt-cells = <3>; 308 interrupts = <1 9 4>; 309 }; 310 311 sysctrl@61840000 { 312 compatible = "socionext,uniphier-sysctrl", 313 "simple-mfd", "syscon"; 314 reg = <0x61840000 0x4000>; 315 316 sys_clk: clock { 317 compatible = "socionext,uniphier-ld20-clock"; 318 #clock-cells = <1>; 319 }; 320 321 sys_rst: reset { 322 compatible = "socionext,uniphier-ld20-reset"; 323 #reset-cells = <1>; 324 }; 325 }; 326 }; 327}; 328 329/include/ "uniphier-pinctrl.dtsi" 330