ARM64: dts: marvell: armada-cp110: Add registers clock for sata node

This extra clock is needed to access the registers of the AHCI SATA
controller used on the Armada 7K/8K SoCs.

The ahci drivers w

ARM64: dts: marvell: armada-cp110: Add registers clock for sata node

This extra clock is needed to access the registers of the AHCI SATA
controller used on the Armada 7K/8K SoCs.

The ahci drivers was already designed to support up to 5 clocks so there
is only need to update the device tree to use it. It was not noticed
until now because of wrong assumption in the clock drivers, but as this
IP really needs 2 clocks, we had to declare both of them.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: use SPDX-License-Identifier for Armada SoCs

Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.

As already pointed on the DT ML, th

arm64: dts: marvell: use SPDX-License-Identifier for Armada SoCs

Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.

As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.

[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: add CP110 uart peripherals

The CP110 component has 4 uart peripherals. All of them use the same clock
gate for slow peripherals that is shared with the i2c and spi peripherals.

arm64: dts: marvell: add CP110 uart peripherals

The CP110 component has 4 uart peripherals. All of them use the same clock
gate for slow peripherals that is shared with the i2c and spi peripherals.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

ARM64: dts: marvell: armada-cp110: Add registers clock for I2C nodes

This extra clock is needed to access the registers of the I2C controller
used on the Armada 7K/8K SoCs.

This follows the changes

ARM64: dts: marvell: armada-cp110: Add registers clock for I2C nodes

This extra clock is needed to access the registers of the I2C controller
used on the Armada 7K/8K SoCs.

This follows the changes already made in the binding documentation (as
well as in the driver) in:
commit 1534156e999735fe0befad958e1447600c0c20e7 ("i2c: mv64xxx: Fix clock
resource by adding an optional bus clock")

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

ARM64: dts: marvell: armada-cp110: Add registers clock for SPI nodes

This extra clock is needed to access the registers of the SPI controller
used on Armada 7K/8K SoCs.

This follows the changes alr

ARM64: dts: marvell: armada-cp110: Add registers clock for SPI nodes

This extra clock is needed to access the registers of the SPI controller
used on Armada 7K/8K SoCs.

This follows the changes already made in the binding documentation (as
well as in the driver) in:
'commit 92ae112e477ac412decc3fdd5c1eeb6c90c266b4 ("spi: orion: Fix clock
resource by adding an optional bus clock")'.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: de-duplicate CP110 description

One concept of Marvell Armada 7K/8K SoCs is that they are made of HW
blocks composed of a variety of IPs (network, PCIe, SATA, XOR, SPI,
I2C, etc.

arm64: dts: marvell: de-duplicate CP110 description

One concept of Marvell Armada 7K/8K SoCs is that they are made of HW
blocks composed of a variety of IPs (network, PCIe, SATA, XOR, SPI,
I2C, etc.), and those HW blocks can be duplicated several times within
a given SoC. The Armada 7K SoC has a single CP110 (so no duplication),
while the Armada 8K SoC has two CP110. In the future, SoCs with more
than 2 CP110s will be introduced.

In current kernel versions, the master CP110 is described in
armada-cp110-master.dtsi and the slave CP110 is described in
armada-cp110-slave.dtsi. Those files are basically exactly the same,
since they describe the same hardware. They only have a few
differences:

- Base address of the registers is different for the "config-space"

- Base address of the PCIe registers, MEM, CONF and IO areas were
different

- Labels (and phandles pointing to them) of the nodes were different
("cpm" prefix in the master CP, "cps" prefix in the slave CP)

This duplication issue has been discussed at the DT workshop [1] in
Prague last October, and we presented on this topic [2]. The solution
of using the C pre-processor to avoid this duplication has been
validated by the people present in this DT workshop, and this patch
simply implements what has been presented.

We handle differences between the master CP and slave CP description
using the C pre-processor, by defining a set of macros with different
values armada-cp110.dtsi is included to instantiate one of the master
or slave CP110.

There are a few aspects that deserve additional explanations:

- PCIe needs to be handled separately because it is not part of the
config-space {...} node, since it has registers outside of the
range covered by config-space {...}.

- We need to defined CP110_BASE, CP110_PCIEx_BASE without 0x, because
they are used for the unit address part of some DT nodes. But since
they are also used for the "reg" property of the same nodes, we
have an ADDRESSIFY() macro that prepends 0x to those values.

We compared the resulting .dtb for armada-8040-db.dtb before and after
this patch is applied, and the result is exactly the same, except for
a few differences:

- the SDHCI controller that was only described in the master CP110 is
now also described in the slave CP110. Even though the SDHCI
controller from the slave CP110 is indeed not usable (as it isn't
wired to the outside world) it is technically part of the silicon,
and therefore it is reasonable to also describe it to be part of
the slave CP110. In addition, if we wanted to get this correct for
the SDHCI controller, we should also do it for the NAND controller,
for which the situation is even more complicated: in a single CP110
configuration (Armada 7K), the usable NAND controller is in the
master CP110, while in a dual CP110 configuration (Armada 8K), the
usable NAND controller is in the slave CP110. Since that would add
a lot of additional complexity for no good reason, and since the IP
blocks are in fact really present in both CPs, we simply describe
them in both CPs at the DT level.

- the cp110-master and cp110-slave nodes are now named cpm and
cps. We could have kept cp110-master and cp110-slave, but that
would have required adding another CP110_xyz define, which didn't
seem very useful.

Note that this commit also gets rid of the armada-cp110-master.dtsi
and armada-cp110-slave.dtsi files, as future SoCs will have more than
2 CPs. Instead, we instantiate the CPs directly from the SoC-specific
.dtsi files, i.e armada-70x0.dtsi and armada-80x0.dtsi.

[1] https://elinux.org/Device_tree_kernel_summit_2017_etherpad
[2] https://elinux.org/images/1/14/DTWorkshop2017-duplicate-data.pdf

[gregory.clement@free-electrons.com: add back the "ARM64: dts: marvell:
Fix clock resources for various node" commit]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

show more ...

arm64: dts: marvell: Prepare the introduction of CP115

CP110 and CP115 are almost the same in terms of features and have a
very limited set of differences. Let's create an armada-cp11x.d

arm64: dts: marvell: Prepare the introduction of CP115

CP110 and CP115 are almost the same in terms of features and have a
very limited set of differences. Let's create an armada-cp11x.dtsi
file which will be used to instantiate both CP110 and CP115
nodes.

The only changes between the two armada-cp11{0,x}.dtsi files are the
following naming in macros: s/CP110/CP11X/.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment

Fix this tiny typo before renaming/changing this file.

Fixes: 72a3713fadfd ("arm64: dts: marvell: de

arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment

Fix this tiny typo before renaming/changing this file.

Fixes: 72a3713fadfd ("arm64: dts: marvell: de-duplicate CP110 description")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes

Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k
based boards.

Signed-off-by: Miquel Raynal <miqu

arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes

Fill-in the missing SATA phys/phy-names DT properties of Armada 7k/8k
based boards.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: Add CP110 COMPHY clocks

Declare the three clocks feeding the COMPHY block.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory C

arm64: dts: marvell: Add CP110 COMPHY clocks

Declare the three clocks feeding the COMPHY block.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: add missing #interrupt-cells property

The GPIO interrupt controllers are missing their required
specified in DT.

Signed-off-by: Russell King <rmk+kernel@arm

arm64: dts: marvell: add missing #interrupt-cells property

The GPIO interrupt controllers are missing their required
specified in DT.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: add interrupt support to cp110 thermal node

Add interrupt properties in the thermal node as well as a critical trip
point in the thermal-zone.

Signed-off-by

arm64: dts: marvell: add interrupt support to cp110 thermal node

Add interrupt properties in the thermal node as well as a critical trip
point in the thermal-zone.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: add CP110 ICU SEI subnode

The ICU handles several interrupt groups, each of them being a subpart
of the ICU node.

Signed-off-by: Miquel Raynal <miquel.rayna

arm64: dts: marvell: add CP110 ICU SEI subnode

The ICU handles several interrupt groups, each of them being a subpart
of the ICU node.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: use new bindings for CP110 interrupts

Create an ICU subnode for the NSR interrupts. This subnode becomes the
CP110 interrupt parent, removing the need for the ICU_GR

arm64: dts: marvell: use new bindings for CP110 interrupts

Create an ICU subnode for the NSR interrupts. This subnode becomes the
CP110 interrupt parent, removing the need for the ICU_GRP_NSR parameter.
Move all DT110 nodes to use these new bindings.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: armada-cp110: describe more PPv2 interrupts

This patch describes 3 additional interrupts per PPv2 port. Those
interrupts will be used later in future versions of the

arm64: dts: marvell: armada-cp110: describe more PPv2 interrupts

This patch describes 3 additional interrupts per PPv2 port. Those
interrupts will be used later in future versions of the Marvell PPv2
driver, and now the device tree description matches the hardware
capabilities.

Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: armada-cp110: change the PPv2 IRQ names

This patch changes the PPv2 IRQ names in the CP110 device tree to match
a corresponding change in the Marvell PPv2 driver. Th

arm64: dts: marvell: armada-cp110: change the PPv2 IRQ names

This patch changes the PPv2 IRQ names in the CP110 device tree to match
a corresponding change in the Marvell PPv2 driver. The reason this was
updated is the IRQ where names after Tx/Rx interrupts, but this is not
true and can be configured. A following patch will add more of them and
the names wouldn't make sense.

Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: add thermal-zone node in cp110 DTSI file

Add a thermal-zone node and fill in all the sensors available in a
cp110 (only one in the thermal IP).

Signed-off-b

arm64: dts: marvell: add thermal-zone node in cp110 DTSI file

Add a thermal-zone node and fill in all the sensors available in a
cp110 (only one in the thermal IP).

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

arm64: dts: marvell: move AP806/CP110 thermal nodes into a new syscon

New bindings impose to declare the thermal IP from within a new syscon.

Signed-off-by: Miquel Raynal <miquel.ra

arm64: dts: marvell: move AP806/CP110 thermal nodes into a new syscon

New bindings impose to declare the thermal IP from within a new syscon.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

Merge tag 'mvebu-dt64-4.19-2' of git://git.infradead.org/linux-mvebu into next/dt

mvebu dt64 for 4.19 (part 2)

Use more specific compatible for the Inside Secure SafeXcel on the

Merge tag 'mvebu-dt64-4.19-2' of git://git.infradead.org/linux-mvebu into next/dt

mvebu dt64 for 4.19 (part 2)

Use more specific compatible for the Inside Secure SafeXcel on the
Armada 37xx and the Armada 7K/8K SoCs.

* tag 'mvebu-dt64-4.19-2' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: armada-37xx: update the crypto engine compatible
arm64: dts: marvell: armada-cp110: update the crypto engine compatible

Signed-off-by: Olof Johansson <olof@lixom.net>

show more ...

arm64: dts: marvell: armada-cp110: update the crypto engine compatible

New compatibles are now supported by the Inside Secure SafeXcel driver.
As they are more specific than the old ones

arm64: dts: marvell: armada-cp110: update the crypto engine compatible

New compatibles are now supported by the Inside Secure SafeXcel driver.
As they are more specific than the old ones, they should be used
whenever possible. This patch updates the Marvell cp110 device tree
accordingly.

Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

Merge tag 'mvebu-fixes-4.17-2' of git://git.infradead.org/linux-mvebu into fixes

mvebu fixes for 4.17 (part 2)

- Use correct size for ICU nodes (irq controller) on Armada 7K/8K

Merge tag 'mvebu-fixes-4.17-2' of git://git.infradead.org/linux-mvebu into fixes

mvebu fixes for 4.17 (part 2)

- Use correct size for ICU nodes (irq controller) on Armada 7K/8K
- Fix "#cooling-cells" property's name on Synology DS116 (Armada 385)

* tag 'mvebu-fixes-4.17-2' of git://git.infradead.org/linux-mvebu:
arm: dts: armada: Fix "#cooling-cells" property's name
arm64: dts: marvell: fix CP110 ICU node size

Signed-off-by: Olof Johansson <olof@lixom.net>

show more ...

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device tree updates from Olof Johansson:
"As always, a large number of DT updates. Too ma

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device tree updates from Olof Johansson:
"As always, a large number of DT updates. Too many to enumerate them
all, but at a glance:

New SoCs introduced in this release:

- Amlogic:
+ Meson 8M2 SoC, a.k.a. S812. A quad Cortex-A9 SoC used in some
set top boxes and other products.

- Mediatek:
+ MT7623A, which is a flavor of the MT7623 family with other
on-chip ethernet options.

- Qualcomm:
+ SDM845, a.k.a Snapdragon 845, an 4+4-core Kryo 385/845
(Cortex-A75/A55 derivative) SoC that's one of the current
high-end mobile SoCs.

It's great to see mainline support for it. So far, you can't do
much with it, since a lot of peripherals are not yet in the DTs
but driver support for USB, GPU and other pieces are starting to
trickle in. This might end up being a well-supported SoC
upstream if the momentum keeps up.

- Renesas:
+ R8A77990, a.k.a R-Car E3, a new automotive
entertainment-targeted SoC. Currently only one Cortex-A53 CPU is
enabled, we are eagerly awaiting more. So far, basic drivers
such as serial, gpios, PMU and ethernet are enabled.
+ R8A77470, a.k.a. RZ/G1C, a new dual Cortex-A7 SoC with PowerVR
GPU. Same here, basic set of drivers such as serial, gpios and
ethernet enabled, and SMP support is also forthcoming.

- STMicroelectronics:
+ STM32F469, very similar tih STM32F429 but with display support

Enhancements to SoCs/platforms (DTS contents, some driver portions
might not be in yet):
- Allwinner sun8i (h3/a33/a83t) SMP, DVFS tweaks, misc
- Amlogic Meson: I2C, UFS, TDM, GPIO external interrupts, MMC resets
- Hisilicon hi3660: Thermal cooling, CPU frequency scaling, mailbox interfaces
- Marvell Berlin2CD: SMP support, thermal sensors
- Mediatek MT7623: Highspeed DMA, audio support
- Qualcomm IPQ8074 PCIe support, MSM8996 UFS support
- Renesas: Watchdog and PMU support across many platforms
- Rockchip RK3399: USB3 OTG support
- Samsung Exynos: Audio-over-HDMI on Odroid X/X2/U3
- STMicro STM32: Lots of peripherals added to STM32MP175C
- Uniphier: Ethernet support

New boards:
- Allwinner A20: Olimex A20-SOM-EVB-eMMC variant
- Allwinner H2+: Libre Computer ALL-H3-CC (h2+ version)
- Allwinner A33: Nintendo NES/SuperNES Classic Edition
- Aspeed: S2600WF, Inventec Lanyang BMC, Portwell Neptune
- Berlin2CD: Valve Steam Link
- Broadcom BCM5301X: Luxul XAP-1610 and XWR-3150 V1
- Broadcom: Raspberry Pi 3 B+
- Mediatek MT7623N and MT7623A: reference boards
- Meson 8M2: Tronsmart MXIII Plus
- NXP i.MX: Engicam i.CoreM6, DHCOM iMX6 SOM, BTicino i.MX6DL Mamoj
- Qualcomm MSM8974: Sony Xperia Z1 Compact support
- Qualcomm SDM845: MTP development board
- Renesas: Ebisu R8A77990 board
- Renesas RZ/G1C: iwg23s: iWave G235-SDB
- TI am335x: Pocketbeagle support"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (448 commits)
ARM: dts: aspeed: Fix hwrng register address
arm64: dts: sprd: whale2: Add the rtc enable clock for watchdog
arm64: dts: sprd: Add GPIO and GPIO keys device nodes
arm64: dts: sprd: fix typo in 'remote-endpoint'
arm64: dts: apq8096-db820c: Removed bt-en-1-8v regulator
arm64: dts: fix regulator property name for wlan pcie endpoint
arm64: dts: qcom: msm8996: Use UFS_GDSC for UFS
ARM: dts: pxa3xx: fix MMC clocks
ARM: pxa: dts: add pin definitions for extended GPIOs
ARM: pxa: dts: add gpio-ranges to gpio controller
ARM: dts: ipq8074: Enable few peripherals for hk01 board
ARM: dts: ipq8074: Add pcie nodes
ARM: dts: ipq8074: Add peripheral nodes
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
ARM: dts: ipq4019: Change the max opp frequency
...

show more ...

arm64: dts: marvell: fix CP110 ICU node size

ICU size in CP110 is not 0x10 but at least 0x440 bytes long (from the
specification).

Fixes: 6ef84a827c37 ("arm64: dts: marvell: ena

arm64: dts: marvell: fix CP110 ICU node size

ICU size in CP110 is not 0x10 but at least 0x440 bytes long (from the
specification).

Fixes: 6ef84a827c37 ("arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K")
Cc: stable@vger.kernel.org
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

ARM64: dts: marvell: armada-cp110: Add mg_core_clk for ethernet node

Marvell PPv2.2 controller present on CP-110 need the extra "mg_core_clk"
clock to avoid system hangs when powering so

ARM64: dts: marvell: armada-cp110: Add mg_core_clk for ethernet node

Marvell PPv2.2 controller present on CP-110 need the extra "mg_core_clk"
clock to avoid system hangs when powering some network interfaces up.

This issue appeared after a recent clock rework on Armada 7K/8K platforms.

This commit adds the new clock and updates the documentation accordingly.

[gregory.clement: use the real first commit to fix and add the cc:stable
flag]
Fixes: e3af9f7c6ece ("RM64: dts: marvell: armada-cp110: Fix clock resources for various node")
Cc: <stable@vger.kernel.org>
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...

ARM64: dts: marvell: armada-cp110: Add clocks for the xmdio node

The Marvell XSMI controller needs 3 clocks to operate correctly :
- The MG clock (clk 5)
- The MG Core clock (clk 6

ARM64: dts: marvell: armada-cp110: Add clocks for the xmdio node

The Marvell XSMI controller needs 3 clocks to operate correctly :
- The MG clock (clk 5)
- The MG Core clock (clk 6)
- The GOP clock (clk 18)

This commit adds them, to avoid system hangs when using these
interfaces.

[gregory.clement: use the real first commit to fix and add the cc:stable
flag]
Fixes: f66b2aff46ea ("arm64: dts: marvell: add xmdio nodes for 7k/8k")
Cc: <stable@vger.kernel.org>
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

show more ...