Revision tags: v4.7.2, v4.4.19, openbmc-4.4-20160819-1, v4.7.1, v4.4.18, v4.4.17, openbmc-4.4-20160804-1, v4.4.16 |
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fa243f64 |
| 27-Jul-2016 |
Ulf Hansson <ulf.hansson@linaro.org> |
mmc: sdhci-pltfm: Drop define for SDHCI_PLTFM_PMOPS
Due to previous changes this define has no longer a purpose. Instead move the sdhci-pltfm drivers over to use the exported struct sdhci_pltfm_pmop
mmc: sdhci-pltfm: Drop define for SDHCI_PLTFM_PMOPS
Due to previous changes this define has no longer a purpose. Instead move the sdhci-pltfm drivers over to use the exported struct sdhci_pltfm_pmops.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.7, openbmc-4.4-20160722-1, openbmc-20160722-1 |
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4f6aa326 |
| 12-Jul-2016 |
Jon Hunter <jonathanh@nvidia.com> |
mmc: tegra: Only advertise UHS modes if IO regulator is present
To support UHS modes for Tegra an external regulator must be present to adjust the IO voltage accordingly. Even if the regulator is no
mmc: tegra: Only advertise UHS modes if IO regulator is present
To support UHS modes for Tegra an external regulator must be present to adjust the IO voltage accordingly. Even if the regulator is not present but the host supports the UHS modes and the device supports the UHS modes, then we will attempt to switch to a high-speed mode. Without an external regulator, Tegra will fail to switch to the high-speed mode.
It has been found that with some SD cards, that once it has been switch to operate at a high-speed mode, all subsequent commands issues to the card will fail and so it will not be possible to switch back to a non high-speed mode and so the SD card initialisation will fail.
The SDHCI core does not require that the host have an external regulator when switching to UHS modes and therefore, the Tegra SDHCI host controller should only advertise the UHS modes as being supported if the regulator for the IO voltage is present. Fortunately, Tegra has a vendor specific register which can be used to control which modes are advertised via the SDHCI_CAPABILITIES register. Hence, if there is no IO voltage regulator available for the Tegra SDHCI host, then don't advertise the UHS modes.
Note that if the regulator is not available, we also don't advertise that the SDHCI is compatible with v3.0 of the SDHCI specification because this will read the SDHCI_CAPABILITIES_1 register which will enable other UHS modes.
This fixes commit 7ad2ed1dfcbe ("mmc: tegra: enable UHS-I modes") which enables UHS mode without checking if the board can support them.
Fixes: 7ad2ed1dfcbe ("mmc: tegra: enable UHS-I modes") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: openbmc-20160713-1, v4.4.15, v4.6.4, v4.6.3, v4.4.14, v4.6.2, v4.4.13, openbmc-20160606-1, v4.6.1, v4.4.12, openbmc-20160521-1, v4.4.11, openbmc-20160518-1, v4.6, v4.4.10, openbmc-20160511-1, openbmc-20160505-1, v4.4.9, v4.4.8 |
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70ad7f7e |
| 13-Apr-2016 |
Jon Hunter <jonathanh@nvidia.com> |
mmc: tegra: Disable UHS-I modes for Tegra124
Tegra124 has been randomly hanging during system suspend when entering the Tegra LP1 low power state. The hang is caused by the Tegra SDHCI driver and li
mmc: tegra: Disable UHS-I modes for Tegra124
Tegra124 has been randomly hanging during system suspend when entering the Tegra LP1 low power state. The hang is caused by the Tegra SDHCI driver and linked to the UHS-I tuning sequence. Disabling the UHS-I modes for Tegra124 prevents any hangs from occurring when entering system suspend.
Unfortunately, the tuning sequence described in the public Tegra documentation is incomplete and on inspection of the current tuning sequence that has been implemented is also incomplete and may cause problems. In the short-term it is safer to disable UHS-I modes for now and fix later because it would be too large of a change to simply patch now. Therefore, disable UHS-I modes for Tegra124.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.4.7, openbmc-20160329-2, openbmc-20160329-1, openbmc-20160321-1, v4.4.6, v4.5, v4.4.5, v4.4.4 |
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e5c63d91 |
| 29-Feb-2016 |
Lucas Stach <dev@lynxeye.de> |
mmc: tegra: implement memcomp pad calibration
The Tegra30+ SDMMC module has memcomp pads that are used to automatically find and set the correct drive strength settings to the sdmmc pads. The calibr
mmc: tegra: implement memcomp pad calibration
The Tegra30+ SDMMC module has memcomp pads that are used to automatically find and set the correct drive strength settings to the sdmmc pads. The calibration needs to be manually kicked off when the card signal voltage is changed, after the card clock is supplied again.
Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> [Ulf: Rebased to fix a trivial compile error] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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3491b690 |
| 29-Feb-2016 |
Lucas Stach <dev@lynxeye.de> |
mmc: tegra: properly disable card clock
The new code to do the clock rate setting externally to the SDMMC module has a shortcut to not propagate changes with a 0 rate to the CAR by simply bailing ou
mmc: tegra: properly disable card clock
The new code to do the clock rate setting externally to the SDMMC module has a shortcut to not propagate changes with a 0 rate to the CAR by simply bailing out. This breaks proper cutting of the card clock. Fix it by directly calling the correct sdhci function.
Fixes: a8e326a911d3 "mmc: tegra: implement module external clock change" Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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7bf037d6 |
| 26-Feb-2016 |
Jon Hunter <jonathanh@nvidia.com> |
mmc: tegra: Disable UHS-I modes for tegra114
SD card support for Tegra114 started failing after commit a8e326a911d3 ("mmc: tegra: implement module external clock change") was merged. This commit was
mmc: tegra: Disable UHS-I modes for tegra114
SD card support for Tegra114 started failing after commit a8e326a911d3 ("mmc: tegra: implement module external clock change") was merged. This commit was part of a series to enable UHS-I modes for Tegra. To workaround this problem for now, disable UHS-I modes for Tegra114 by separating the soc data structures for Tegra114 and Tegra124 so that UHS-I is still enabled for Tegra124 but not Tegra114.
Fixes: a8e326a911d3 ("mmc: tegra: implement module external clock change") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Lucas Stach <dev@lynxeye.de> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.4.3, openbmc-20160222-1, v4.4.2 |
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0734e79c |
| 16-Feb-2016 |
Jisheng Zhang <jszhang@marvell.com> |
mmc: sdhci-tegra: use sdhci_pltfm_init for private allocation
Commit 0e748234293f ("mmc: sdhci: Add size for caller in init+register") allows users of sdhci_pltfm to allocate private space in calls
mmc: sdhci-tegra: use sdhci_pltfm_init for private allocation
Commit 0e748234293f ("mmc: sdhci: Add size for caller in init+register") allows users of sdhci_pltfm to allocate private space in calls to sdhci_pltfm_init+sdhci_pltfm_register. This patch migrates sdhci-tegra to this allocation.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: openbmc-20160212-1, openbmc-20160210-1, openbmc-20160202-2, openbmc-20160202-1, v4.4.1, openbmc-20160127-1, openbmc-20160120-1, v4.4 |
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1b84def8 |
| 22-Dec-2015 |
Lucas Stach <dev@lynxeye.de> |
mmc: tegra: use correct accessor for misc ctrl register
The misc control register is 32bit wide, the used readw/writew accessors only mainipulate the low 16bit of this register. It currently doesn't
mmc: tegra: use correct accessor for misc ctrl register
The misc control register is 32bit wide, the used readw/writew accessors only mainipulate the low 16bit of this register. It currently doesn't matter as all the bit changed are located in the lower half, but together with the u32 variable used to hold the contents of the register it is seriously confusing.
Switch to 32bit accessors to avoid any future breakage.
Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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7ad2ed1d |
| 22-Dec-2015 |
Lucas Stach <dev@lynxeye.de> |
mmc: tegra: enable UHS-I modes
Keep the quirk bits, as Tegra30 and Tegra114 host have different levels of support for UHS-I modes and so need different spare bits to be set, but change the logic to
mmc: tegra: enable UHS-I modes
Keep the quirk bits, as Tegra30 and Tegra114 host have different levels of support for UHS-I modes and so need different spare bits to be set, but change the logic to be positive.
Tegra210 needs a different tuning sequence than Tegra30+. Disable UHS modes until support for this is properly added.
Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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c3c2384c |
| 22-Dec-2015 |
Lucas Stach <dev@lynxeye.de> |
mmc: tegra: implement UHS tuning
This implements the UHS tuning sequence in a similar way to the one contained in the TRM. It deviates in the way how to check if the tap value is passing, by using t
mmc: tegra: implement UHS tuning
This implements the UHS tuning sequence in a similar way to the one contained in the TRM. It deviates in the way how to check if the tap value is passing, by using the common Linux MMC function, which does not only check for data CRC errors, but also if the received block pattern is correct.
Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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74cd42bc |
| 22-Dec-2015 |
Lucas Stach <dev@lynxeye.de> |
mmc: tegra: disable SPI_MODE_CLKEN
The Tegra30 and up TRM states that this bit should always be programmed to 0 by driver software.
Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Ulf Ha
mmc: tegra: disable SPI_MODE_CLKEN
The Tegra30 and up TRM states that this bit should always be programmed to 0 by driver software.
Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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a8e326a9 |
| 22-Dec-2015 |
Lucas Stach <dev@lynxeye.de> |
mmc: tegra: implement module external clock change
Allow the the driver to change the clock supplied from the CAR directly, minimizing the need to divide the clock inside the SDMMC module itself.
T
mmc: tegra: implement module external clock change
Allow the the driver to change the clock supplied from the CAR directly, minimizing the need to divide the clock inside the SDMMC module itself.
This allows for higher clock speeds than the default 48MHz supplied to the module and is a prerequisite to support DDR signaling modes, where the Tegra host needs to be run with a fixed internal divider of 2 for data to be sampled correctly. (Tegra K1 TRM v03p chapter 29.7.1.1)
Also enable the broken preset value quirk as the preset values need to be adapted to the changed clocking. While Tegra114+ allows this through vendor registers, there is no such way for Tegra30. Takes the easy way out and keep things consistent between the different SoC generations by flagging the preset registers as unusable.
Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: openbmc-20151217-1, openbmc-20151210-1, openbmc-20151202-1, openbmc-20151123-1, openbmc-20151118-1 |
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b5a84ecf |
| 16-Nov-2015 |
Thierry Reding <treding@nvidia.com> |
mmc: tegra: Add Tegra210 support
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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d49d19c2 |
| 16-Nov-2015 |
Thierry Reding <treding@nvidia.com> |
mmc: tegra: Constify SoC data
The data in the SoC description structures is static and can therefore reside in read-only memory.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ul
mmc: tegra: Constify SoC data
The data in the SoC description structures is static and can therefore reside in read-only memory.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: openbmc-20151104-1, v4.3, openbmc-20151102-1, openbmc-20151028-1, v4.3-rc1, v4.2, v4.2-rc8, v4.2-rc7, v4.2-rc6, v4.2-rc5, v4.2-rc4, v4.2-rc3, v4.2-rc2, v4.2-rc1, v4.1, v4.1-rc8, v4.1-rc7, v4.1-rc6, v4.1-rc5, v4.1-rc4, v4.1-rc3, v4.1-rc2, v4.1-rc1, v4.0, v4.0-rc7 |
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2391b340 |
| 30-Mar-2015 |
Mylene JOSSERAND <josserand.mylene@gmail.com> |
mmc: sdhci-tegra: convert to use GPIO descriptors
Modify the driver to handle GPIOs using the descriptor API.
Signed-off-by: Mylene JOSSERAND <josserand.mylene@gmail.com> Reviewed-by: Alexandre Cou
mmc: sdhci-tegra: convert to use GPIO descriptors
Modify the driver to handle GPIOs using the descriptor API.
Signed-off-by: Mylene JOSSERAND <josserand.mylene@gmail.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.0-rc6, v4.0-rc5, v4.0-rc4, v4.0-rc3, v4.0-rc2, v4.0-rc1 |
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01df7ecd |
| 11-Feb-2015 |
Rhyland Klein <rklein@nvidia.com> |
mmc: tegra: Optimize write_w path for tegra114 and later
Setup a different set of sdhci_ops for tegra114 and later so that the write_w callback is only used on tegra114. This allows us to remove the
mmc: tegra: Optimize write_w path for tegra114 and later
Setup a different set of sdhci_ops for tegra114 and later so that the write_w callback is only used on tegra114. This allows us to remove the NVQUIRK_SHADOW_XFER_MODE_REG and simply the logic in tegra_sdhci_writew.
Suggested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Acked-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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caebcae9 |
| 27-Feb-2015 |
Kevin Hao <haokexin@gmail.com> |
mmc: sdhci: set the .remove to sdhci_pltfm_unregister()
In these drivers, the driver specific .remove function just a simple wrapper of function sdhci_pltfm_unregister(). So remove these wrappers an
mmc: sdhci: set the .remove to sdhci_pltfm_unregister()
In these drivers, the driver specific .remove function just a simple wrapper of function sdhci_pltfm_unregister(). So remove these wrappers and just set .remove to sdhci_pltfm_unregister().
Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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83eacdfa |
| 27-Feb-2015 |
Kevin Hao <haokexin@gmail.com> |
mmc: sdhci: disable the clock in sdhci_pltfm_unregister()
So we can avoid to sprinkle the clk_disable_unprepare() in many drivers.
Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Ulf H
mmc: sdhci: disable the clock in sdhci_pltfm_unregister()
So we can avoid to sprinkle the clk_disable_unprepare() in many drivers.
Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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e4f79d9c |
| 27-Feb-2015 |
Kevin Hao <haokexin@gmail.com> |
mmc: tegra: use devm help functions to get the clk and gpio
Simplify the error and remove path.
Signed-off-by: Kevin Hao <haokexin@gmail.com> Acked-by: Alexandre Courbot <acourbot@nvidia.com> Signe
mmc: tegra: use devm help functions to get the clk and gpio
Simplify the error and remove path.
Signed-off-by: Kevin Hao <haokexin@gmail.com> Acked-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v3.19, v3.19-rc7 |
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352ee868 |
| 28-Jan-2015 |
Pavan Kunapuli <pkunapuli@nvidia.com> |
mmc: tegra: Write xfer_mode, CMD regs in together
If there is a gap between xfer mode and command register writes, tegra SDMMC controller can sometimes issue a spurious command before the CMD regist
mmc: tegra: Write xfer_mode, CMD regs in together
If there is a gap between xfer mode and command register writes, tegra SDMMC controller can sometimes issue a spurious command before the CMD register is written. To avoid this, these two registers need to be written together in a single write operation.
This is implemented as an NVQUIRK as it applies to T114, T124 and T132.
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v3.19-rc6, v3.19-rc5, v3.19-rc4, v3.19-rc3, v3.19-rc2, v3.19-rc1, v3.18, v3.18-rc7, v3.18-rc6, v3.18-rc5, v3.18-rc4, v3.18-rc3, v3.18-rc2, v3.18-rc1, v3.17, v3.17-rc7, v3.17-rc6, v3.17-rc5, v3.17-rc4, v3.17-rc3, v3.17-rc2, v3.17-rc1 |
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2137f5d3 |
| 12-Aug-2014 |
Peter Griffin <peter.griffin@linaro.org> |
mmc: remove .owner field for drivers using module_platform_driver
This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platfor
mmc: remove .owner field for drivers using module_platform_driver
This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platform_driver_register anyway.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v3.16, v3.16-rc7, v3.16-rc6, v3.16-rc5 |
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1b3f626e |
| 07-Jul-2014 |
Thierry Reding <treding@nvidia.com> |
mmc: tegra: Do not include asm/gpio.h
This doesn't seem to be used any longer and removing the include fixes 64-bit ARM builds.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf
mmc: tegra: Do not include asm/gpio.h
This doesn't seem to be used any longer and removing the include fixes 64-bit ARM builds.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v3.16-rc4, v3.16-rc3, v3.16-rc2, v3.16-rc1, v3.15, v3.15-rc8, v3.15-rc7 |
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f9260355 |
| 22-May-2014 |
Andrew Bresticker <abrestic@chromium.org> |
mmc: tegra: fix reporting of base clock frequency
Tegra SDHCI controllers, by default, report a base clock frequency of 208Mhz in SDHCI_CAPABILTIES which may or may not be equal to the actual base c
mmc: tegra: fix reporting of base clock frequency
Tegra SDHCI controllers, by default, report a base clock frequency of 208Mhz in SDHCI_CAPABILTIES which may or may not be equal to the actual base clock frequency. This is because the clock rate is configured by the clock controller, which is external to the SD/MMC controller. Since the SD/MMC controller has no knowledge of how this clock is configured, it will simply report the maximum frequency. While the reported value can be overridden by setting BASE_CLK_FREQ in VENDOR_CLOCK_CTRL on Tegra30 and later SoCs, just set CAP_CLOCK_BASE_BROKEN and supply sdhci_pltfm_clk_get_max_clock(), which simply does a clk_get_rate(), as the get_max_clock() callback.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
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3145351a |
| 22-May-2014 |
Andrew Bresticker <abrestic@chromium.org> |
mmc: tegra: disable UHS modes
Program TEGRA_SDHCI_VENDOR_MISC_CTRL so that UHS modes aren't advertised in SDHCI_CAPABILITIES_1. While the Tegra SDHCI controller does support these modes, they requi
mmc: tegra: disable UHS modes
Program TEGRA_SDHCI_VENDOR_MISC_CTRL so that UHS modes aren't advertised in SDHCI_CAPABILITIES_1. While the Tegra SDHCI controller does support these modes, they require Tegra-specific tuning and calibration routines which the driver does not support yet.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
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Revision tags: v3.15-rc6, v3.15-rc5, v3.15-rc4, v3.15-rc3 |
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b4f3b7c8 |
| 25-Apr-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
mmc: sdhci-tegra: get rid of special PRESENT_STATE register handling
sdhci-tegra provides a get_ro method, which overrides the checking of the write protect bit in the PRESENT_STATE register in sdhc
mmc: sdhci-tegra: get rid of special PRESENT_STATE register handling
sdhci-tegra provides a get_ro method, which overrides the checking of the write protect bit in the PRESENT_STATE register in sdhci.c:
if (host->flags & SDHCI_DEVICE_DEAD) is_readonly = 0; else if (host->ops->get_ro) is_readonly = host->ops->get_ro(host); else is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_WRITE_PROTECT);
This means it's pointless detecting accesses to this register and manually setting the SDHCI_WRITE_PROTECT as it has no effect.
This means that the whole of tegra_sdhci_readl() can be removed and we can use the builtin sdhci readl functionality here.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
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