1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/err.h> 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/mmc/card.h> 24 #include <linux/mmc/host.h> 25 #include <linux/mmc/mmc.h> 26 #include <linux/mmc/slot-gpio.h> 27 #include <linux/gpio/consumer.h> 28 29 #include "sdhci-pltfm.h" 30 31 /* Tegra SDHOST controller vendor register definitions */ 32 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 33 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 34 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 35 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 36 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 37 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 38 39 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 40 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 41 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 42 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 43 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 44 45 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 46 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 47 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 48 #define NVQUIRK_ENABLE_SDR50 BIT(3) 49 #define NVQUIRK_ENABLE_SDR104 BIT(4) 50 #define NVQUIRK_ENABLE_DDR50 BIT(5) 51 52 struct sdhci_tegra_soc_data { 53 const struct sdhci_pltfm_data *pdata; 54 u32 nvquirks; 55 }; 56 57 struct sdhci_tegra { 58 const struct sdhci_tegra_soc_data *soc_data; 59 struct gpio_desc *power_gpio; 60 bool ddr_signaling; 61 }; 62 63 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 64 { 65 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 66 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 67 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 68 69 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 70 (reg == SDHCI_HOST_VERSION))) { 71 /* Erratum: Version register is invalid in HW. */ 72 return SDHCI_SPEC_200; 73 } 74 75 return readw(host->ioaddr + reg); 76 } 77 78 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 79 { 80 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 81 82 switch (reg) { 83 case SDHCI_TRANSFER_MODE: 84 /* 85 * Postpone this write, we must do it together with a 86 * command write that is down below. 87 */ 88 pltfm_host->xfer_mode_shadow = val; 89 return; 90 case SDHCI_COMMAND: 91 writel((val << 16) | pltfm_host->xfer_mode_shadow, 92 host->ioaddr + SDHCI_TRANSFER_MODE); 93 return; 94 } 95 96 writew(val, host->ioaddr + reg); 97 } 98 99 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 100 { 101 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 102 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 103 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 104 105 /* Seems like we're getting spurious timeout and crc errors, so 106 * disable signalling of them. In case of real errors software 107 * timers should take care of eventually detecting them. 108 */ 109 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 110 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 111 112 writel(val, host->ioaddr + reg); 113 114 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 115 (reg == SDHCI_INT_ENABLE))) { 116 /* Erratum: Must enable block gap interrupt detection */ 117 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 118 if (val & SDHCI_INT_CARD_INT) 119 gap_ctrl |= 0x8; 120 else 121 gap_ctrl &= ~0x8; 122 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 123 } 124 } 125 126 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 127 { 128 return mmc_gpio_get_ro(host->mmc); 129 } 130 131 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 132 { 133 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 134 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 135 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 136 u32 misc_ctrl, clk_ctrl; 137 138 sdhci_reset(host, mask); 139 140 if (!(mask & SDHCI_RESET_ALL)) 141 return; 142 143 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 144 /* Erratum: Enable SDHCI spec v3.00 support */ 145 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 146 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 147 /* Advertise UHS modes as supported by host */ 148 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 149 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 150 else 151 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50; 152 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 153 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 154 else 155 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50; 156 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 157 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 158 else 159 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104; 160 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 161 162 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 163 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 164 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 165 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 166 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 167 168 tegra_host->ddr_signaling = false; 169 } 170 171 static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) 172 { 173 u32 ctrl; 174 175 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 176 if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) && 177 (bus_width == MMC_BUS_WIDTH_8)) { 178 ctrl &= ~SDHCI_CTRL_4BITBUS; 179 ctrl |= SDHCI_CTRL_8BITBUS; 180 } else { 181 ctrl &= ~SDHCI_CTRL_8BITBUS; 182 if (bus_width == MMC_BUS_WIDTH_4) 183 ctrl |= SDHCI_CTRL_4BITBUS; 184 else 185 ctrl &= ~SDHCI_CTRL_4BITBUS; 186 } 187 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 188 } 189 190 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 191 { 192 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 193 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 194 unsigned long host_clk; 195 196 if (!clock) 197 return sdhci_set_clock(host, clock); 198 199 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 200 clk_set_rate(pltfm_host->clk, host_clk); 201 host->max_clk = clk_get_rate(pltfm_host->clk); 202 203 return sdhci_set_clock(host, clock); 204 } 205 206 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 207 unsigned timing) 208 { 209 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 210 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 211 212 if (timing == MMC_TIMING_UHS_DDR50) 213 tegra_host->ddr_signaling = true; 214 215 return sdhci_set_uhs_signaling(host, timing); 216 } 217 218 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 219 { 220 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 221 222 /* 223 * DDR modes require the host to run at double the card frequency, so 224 * the maximum rate we can support is half of the module input clock. 225 */ 226 return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2; 227 } 228 229 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 230 { 231 u32 reg; 232 233 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 234 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 235 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 236 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 237 } 238 239 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 240 { 241 unsigned int min, max; 242 243 /* 244 * Start search for minimum tap value at 10, as smaller values are 245 * may wrongly be reported as working but fail at higher speeds, 246 * according to the TRM. 247 */ 248 min = 10; 249 while (min < 255) { 250 tegra_sdhci_set_tap(host, min); 251 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 252 break; 253 min++; 254 } 255 256 /* Find the maximum tap value that still passes. */ 257 max = min + 1; 258 while (max < 255) { 259 tegra_sdhci_set_tap(host, max); 260 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 261 max--; 262 break; 263 } 264 max++; 265 } 266 267 /* The TRM states the ideal tap value is at 75% in the passing range. */ 268 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 269 270 return mmc_send_tuning(host->mmc, opcode, NULL); 271 } 272 273 static const struct sdhci_ops tegra_sdhci_ops = { 274 .get_ro = tegra_sdhci_get_ro, 275 .read_w = tegra_sdhci_readw, 276 .write_l = tegra_sdhci_writel, 277 .set_clock = tegra_sdhci_set_clock, 278 .set_bus_width = tegra_sdhci_set_bus_width, 279 .reset = tegra_sdhci_reset, 280 .platform_execute_tuning = tegra_sdhci_execute_tuning, 281 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 282 .get_max_clock = tegra_sdhci_get_max_clock, 283 }; 284 285 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 286 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 287 SDHCI_QUIRK_SINGLE_POWER_WRITE | 288 SDHCI_QUIRK_NO_HISPD_BIT | 289 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 290 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 291 .ops = &tegra_sdhci_ops, 292 }; 293 294 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 295 .pdata = &sdhci_tegra20_pdata, 296 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 297 NVQUIRK_ENABLE_BLOCK_GAP_DET, 298 }; 299 300 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 301 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 302 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 303 SDHCI_QUIRK_SINGLE_POWER_WRITE | 304 SDHCI_QUIRK_NO_HISPD_BIT | 305 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 306 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 307 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 308 .ops = &tegra_sdhci_ops, 309 }; 310 311 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 312 .pdata = &sdhci_tegra30_pdata, 313 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 314 NVQUIRK_ENABLE_SDR50 | 315 NVQUIRK_ENABLE_SDR104, 316 }; 317 318 static const struct sdhci_ops tegra114_sdhci_ops = { 319 .get_ro = tegra_sdhci_get_ro, 320 .read_w = tegra_sdhci_readw, 321 .write_w = tegra_sdhci_writew, 322 .write_l = tegra_sdhci_writel, 323 .set_clock = tegra_sdhci_set_clock, 324 .set_bus_width = tegra_sdhci_set_bus_width, 325 .reset = tegra_sdhci_reset, 326 .platform_execute_tuning = tegra_sdhci_execute_tuning, 327 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 328 .get_max_clock = tegra_sdhci_get_max_clock, 329 }; 330 331 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 332 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 333 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 334 SDHCI_QUIRK_SINGLE_POWER_WRITE | 335 SDHCI_QUIRK_NO_HISPD_BIT | 336 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 337 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 338 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 339 .ops = &tegra114_sdhci_ops, 340 }; 341 342 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 343 .pdata = &sdhci_tegra114_pdata, 344 }; 345 346 static const struct sdhci_tegra_soc_data soc_data_tegra124 = { 347 .pdata = &sdhci_tegra114_pdata, 348 .nvquirks = NVQUIRK_ENABLE_SDR50 | 349 NVQUIRK_ENABLE_DDR50 | 350 NVQUIRK_ENABLE_SDR104, 351 }; 352 353 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 354 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 355 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 356 SDHCI_QUIRK_SINGLE_POWER_WRITE | 357 SDHCI_QUIRK_NO_HISPD_BIT | 358 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 359 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 360 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 361 .ops = &tegra114_sdhci_ops, 362 }; 363 364 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 365 .pdata = &sdhci_tegra210_pdata, 366 }; 367 368 static const struct of_device_id sdhci_tegra_dt_match[] = { 369 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 370 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 }, 371 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 372 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 373 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 374 {} 375 }; 376 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 377 378 static int sdhci_tegra_probe(struct platform_device *pdev) 379 { 380 const struct of_device_id *match; 381 const struct sdhci_tegra_soc_data *soc_data; 382 struct sdhci_host *host; 383 struct sdhci_pltfm_host *pltfm_host; 384 struct sdhci_tegra *tegra_host; 385 struct clk *clk; 386 int rc; 387 388 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 389 if (!match) 390 return -EINVAL; 391 soc_data = match->data; 392 393 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 394 if (IS_ERR(host)) 395 return PTR_ERR(host); 396 pltfm_host = sdhci_priv(host); 397 398 tegra_host = sdhci_pltfm_priv(pltfm_host); 399 tegra_host->ddr_signaling = false; 400 tegra_host->soc_data = soc_data; 401 402 rc = mmc_of_parse(host->mmc); 403 if (rc) 404 goto err_parse_dt; 405 406 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 407 host->mmc->caps |= MMC_CAP_1_8V_DDR; 408 409 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 410 GPIOD_OUT_HIGH); 411 if (IS_ERR(tegra_host->power_gpio)) { 412 rc = PTR_ERR(tegra_host->power_gpio); 413 goto err_power_req; 414 } 415 416 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 417 if (IS_ERR(clk)) { 418 dev_err(mmc_dev(host->mmc), "clk err\n"); 419 rc = PTR_ERR(clk); 420 goto err_clk_get; 421 } 422 clk_prepare_enable(clk); 423 pltfm_host->clk = clk; 424 425 rc = sdhci_add_host(host); 426 if (rc) 427 goto err_add_host; 428 429 return 0; 430 431 err_add_host: 432 clk_disable_unprepare(pltfm_host->clk); 433 err_clk_get: 434 err_power_req: 435 err_parse_dt: 436 sdhci_pltfm_free(pdev); 437 return rc; 438 } 439 440 static struct platform_driver sdhci_tegra_driver = { 441 .driver = { 442 .name = "sdhci-tegra", 443 .of_match_table = sdhci_tegra_dt_match, 444 .pm = SDHCI_PLTFM_PMOPS, 445 }, 446 .probe = sdhci_tegra_probe, 447 .remove = sdhci_pltfm_unregister, 448 }; 449 450 module_platform_driver(sdhci_tegra_driver); 451 452 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 453 MODULE_AUTHOR("Google, Inc."); 454 MODULE_LICENSE("GPL v2"); 455