1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/err.h> 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/mmc/card.h> 24 #include <linux/mmc/host.h> 25 #include <linux/mmc/mmc.h> 26 #include <linux/mmc/slot-gpio.h> 27 #include <linux/gpio/consumer.h> 28 29 #include "sdhci-pltfm.h" 30 31 /* Tegra SDHOST controller vendor register definitions */ 32 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 33 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 34 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 35 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 36 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 37 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 38 39 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 40 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 41 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 42 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 43 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 44 45 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 46 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 47 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 48 #define NVQUIRK_DISABLE_SDR50 BIT(3) 49 #define NVQUIRK_DISABLE_SDR104 BIT(4) 50 #define NVQUIRK_DISABLE_DDR50 BIT(5) 51 52 struct sdhci_tegra_soc_data { 53 const struct sdhci_pltfm_data *pdata; 54 u32 nvquirks; 55 }; 56 57 struct sdhci_tegra { 58 const struct sdhci_tegra_soc_data *soc_data; 59 struct gpio_desc *power_gpio; 60 bool ddr_signaling; 61 }; 62 63 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 64 { 65 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 66 struct sdhci_tegra *tegra_host = pltfm_host->priv; 67 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 68 69 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 70 (reg == SDHCI_HOST_VERSION))) { 71 /* Erratum: Version register is invalid in HW. */ 72 return SDHCI_SPEC_200; 73 } 74 75 return readw(host->ioaddr + reg); 76 } 77 78 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 79 { 80 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 81 82 switch (reg) { 83 case SDHCI_TRANSFER_MODE: 84 /* 85 * Postpone this write, we must do it together with a 86 * command write that is down below. 87 */ 88 pltfm_host->xfer_mode_shadow = val; 89 return; 90 case SDHCI_COMMAND: 91 writel((val << 16) | pltfm_host->xfer_mode_shadow, 92 host->ioaddr + SDHCI_TRANSFER_MODE); 93 return; 94 } 95 96 writew(val, host->ioaddr + reg); 97 } 98 99 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 100 { 101 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 102 struct sdhci_tegra *tegra_host = pltfm_host->priv; 103 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 104 105 /* Seems like we're getting spurious timeout and crc errors, so 106 * disable signalling of them. In case of real errors software 107 * timers should take care of eventually detecting them. 108 */ 109 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 110 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 111 112 writel(val, host->ioaddr + reg); 113 114 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 115 (reg == SDHCI_INT_ENABLE))) { 116 /* Erratum: Must enable block gap interrupt detection */ 117 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 118 if (val & SDHCI_INT_CARD_INT) 119 gap_ctrl |= 0x8; 120 else 121 gap_ctrl &= ~0x8; 122 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 123 } 124 } 125 126 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 127 { 128 return mmc_gpio_get_ro(host->mmc); 129 } 130 131 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 132 { 133 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 134 struct sdhci_tegra *tegra_host = pltfm_host->priv; 135 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 136 u32 misc_ctrl, clk_ctrl; 137 138 sdhci_reset(host, mask); 139 140 if (!(mask & SDHCI_RESET_ALL)) 141 return; 142 143 misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 144 /* Erratum: Enable SDHCI spec v3.00 support */ 145 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 146 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 147 /* Don't advertise UHS modes which aren't supported yet */ 148 if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50) 149 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50; 150 if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50) 151 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50; 152 if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104) 153 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104; 154 sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 155 156 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 157 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 158 if (!(soc_data->nvquirks & NVQUIRK_DISABLE_SDR50)) 159 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 160 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 161 162 tegra_host->ddr_signaling = false; 163 } 164 165 static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) 166 { 167 u32 ctrl; 168 169 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 170 if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) && 171 (bus_width == MMC_BUS_WIDTH_8)) { 172 ctrl &= ~SDHCI_CTRL_4BITBUS; 173 ctrl |= SDHCI_CTRL_8BITBUS; 174 } else { 175 ctrl &= ~SDHCI_CTRL_8BITBUS; 176 if (bus_width == MMC_BUS_WIDTH_4) 177 ctrl |= SDHCI_CTRL_4BITBUS; 178 else 179 ctrl &= ~SDHCI_CTRL_4BITBUS; 180 } 181 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 182 } 183 184 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 185 { 186 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 187 struct sdhci_tegra *tegra_host = pltfm_host->priv; 188 unsigned long host_clk; 189 190 if (!clock) 191 return; 192 193 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 194 clk_set_rate(pltfm_host->clk, host_clk); 195 host->max_clk = clk_get_rate(pltfm_host->clk); 196 197 return sdhci_set_clock(host, clock); 198 } 199 200 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 201 unsigned timing) 202 { 203 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 204 struct sdhci_tegra *tegra_host = pltfm_host->priv; 205 206 if (timing == MMC_TIMING_UHS_DDR50) 207 tegra_host->ddr_signaling = true; 208 209 return sdhci_set_uhs_signaling(host, timing); 210 } 211 212 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 213 { 214 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 215 216 /* 217 * DDR modes require the host to run at double the card frequency, so 218 * the maximum rate we can support is half of the module input clock. 219 */ 220 return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2; 221 } 222 223 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 224 { 225 u32 reg; 226 227 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 228 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 229 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 230 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 231 } 232 233 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 234 { 235 unsigned int min, max; 236 237 /* 238 * Start search for minimum tap value at 10, as smaller values are 239 * may wrongly be reported as working but fail at higher speeds, 240 * according to the TRM. 241 */ 242 min = 10; 243 while (min < 255) { 244 tegra_sdhci_set_tap(host, min); 245 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 246 break; 247 min++; 248 } 249 250 /* Find the maximum tap value that still passes. */ 251 max = min + 1; 252 while (max < 255) { 253 tegra_sdhci_set_tap(host, max); 254 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 255 max--; 256 break; 257 } 258 max++; 259 } 260 261 /* The TRM states the ideal tap value is at 75% in the passing range. */ 262 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 263 264 return mmc_send_tuning(host->mmc, opcode, NULL); 265 } 266 267 static const struct sdhci_ops tegra_sdhci_ops = { 268 .get_ro = tegra_sdhci_get_ro, 269 .read_w = tegra_sdhci_readw, 270 .write_l = tegra_sdhci_writel, 271 .set_clock = tegra_sdhci_set_clock, 272 .set_bus_width = tegra_sdhci_set_bus_width, 273 .reset = tegra_sdhci_reset, 274 .platform_execute_tuning = tegra_sdhci_execute_tuning, 275 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 276 .get_max_clock = tegra_sdhci_get_max_clock, 277 }; 278 279 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 280 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 281 SDHCI_QUIRK_SINGLE_POWER_WRITE | 282 SDHCI_QUIRK_NO_HISPD_BIT | 283 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 284 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 285 .ops = &tegra_sdhci_ops, 286 }; 287 288 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 289 .pdata = &sdhci_tegra20_pdata, 290 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 291 NVQUIRK_ENABLE_BLOCK_GAP_DET, 292 }; 293 294 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 295 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 296 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 297 SDHCI_QUIRK_SINGLE_POWER_WRITE | 298 SDHCI_QUIRK_NO_HISPD_BIT | 299 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 300 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 301 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 302 .ops = &tegra_sdhci_ops, 303 }; 304 305 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 306 .pdata = &sdhci_tegra30_pdata, 307 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 308 NVQUIRK_DISABLE_SDR50 | 309 NVQUIRK_DISABLE_SDR104, 310 }; 311 312 static const struct sdhci_ops tegra114_sdhci_ops = { 313 .get_ro = tegra_sdhci_get_ro, 314 .read_w = tegra_sdhci_readw, 315 .write_w = tegra_sdhci_writew, 316 .write_l = tegra_sdhci_writel, 317 .set_clock = tegra_sdhci_set_clock, 318 .set_bus_width = tegra_sdhci_set_bus_width, 319 .reset = tegra_sdhci_reset, 320 .platform_execute_tuning = tegra_sdhci_execute_tuning, 321 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 322 .get_max_clock = tegra_sdhci_get_max_clock, 323 }; 324 325 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 326 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 327 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 328 SDHCI_QUIRK_SINGLE_POWER_WRITE | 329 SDHCI_QUIRK_NO_HISPD_BIT | 330 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 331 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 332 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 333 .ops = &tegra114_sdhci_ops, 334 }; 335 336 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 337 .pdata = &sdhci_tegra114_pdata, 338 .nvquirks = NVQUIRK_DISABLE_SDR50 | 339 NVQUIRK_DISABLE_DDR50 | 340 NVQUIRK_DISABLE_SDR104, 341 }; 342 343 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 344 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 345 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 346 SDHCI_QUIRK_SINGLE_POWER_WRITE | 347 SDHCI_QUIRK_NO_HISPD_BIT | 348 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 349 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 350 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 351 .ops = &tegra114_sdhci_ops, 352 }; 353 354 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 355 .pdata = &sdhci_tegra210_pdata, 356 .nvquirks = NVQUIRK_DISABLE_SDR50 | 357 NVQUIRK_DISABLE_DDR50 | 358 NVQUIRK_DISABLE_SDR104, 359 }; 360 361 static const struct of_device_id sdhci_tegra_dt_match[] = { 362 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 363 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 }, 364 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 365 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 366 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 367 {} 368 }; 369 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 370 371 static int sdhci_tegra_probe(struct platform_device *pdev) 372 { 373 const struct of_device_id *match; 374 const struct sdhci_tegra_soc_data *soc_data; 375 struct sdhci_host *host; 376 struct sdhci_pltfm_host *pltfm_host; 377 struct sdhci_tegra *tegra_host; 378 struct clk *clk; 379 int rc; 380 381 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 382 if (!match) 383 return -EINVAL; 384 soc_data = match->data; 385 386 host = sdhci_pltfm_init(pdev, soc_data->pdata, 0); 387 if (IS_ERR(host)) 388 return PTR_ERR(host); 389 pltfm_host = sdhci_priv(host); 390 391 tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL); 392 if (!tegra_host) { 393 dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n"); 394 rc = -ENOMEM; 395 goto err_alloc_tegra_host; 396 } 397 tegra_host->ddr_signaling = false; 398 tegra_host->soc_data = soc_data; 399 pltfm_host->priv = tegra_host; 400 401 rc = mmc_of_parse(host->mmc); 402 if (rc) 403 goto err_parse_dt; 404 405 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_DISABLE_DDR50)) 406 host->mmc->caps |= MMC_CAP_1_8V_DDR; 407 408 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 409 GPIOD_OUT_HIGH); 410 if (IS_ERR(tegra_host->power_gpio)) { 411 rc = PTR_ERR(tegra_host->power_gpio); 412 goto err_power_req; 413 } 414 415 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 416 if (IS_ERR(clk)) { 417 dev_err(mmc_dev(host->mmc), "clk err\n"); 418 rc = PTR_ERR(clk); 419 goto err_clk_get; 420 } 421 clk_prepare_enable(clk); 422 pltfm_host->clk = clk; 423 424 rc = sdhci_add_host(host); 425 if (rc) 426 goto err_add_host; 427 428 return 0; 429 430 err_add_host: 431 clk_disable_unprepare(pltfm_host->clk); 432 err_clk_get: 433 err_power_req: 434 err_parse_dt: 435 err_alloc_tegra_host: 436 sdhci_pltfm_free(pdev); 437 return rc; 438 } 439 440 static struct platform_driver sdhci_tegra_driver = { 441 .driver = { 442 .name = "sdhci-tegra", 443 .of_match_table = sdhci_tegra_dt_match, 444 .pm = SDHCI_PLTFM_PMOPS, 445 }, 446 .probe = sdhci_tegra_probe, 447 .remove = sdhci_pltfm_unregister, 448 }; 449 450 module_platform_driver(sdhci_tegra_driver); 451 452 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 453 MODULE_AUTHOR("Google, Inc."); 454 MODULE_LICENSE("GPL v2"); 455