1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/err.h> 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/of_gpio.h> 24 #include <linux/gpio.h> 25 #include <linux/mmc/card.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/slot-gpio.h> 28 29 #include "sdhci-pltfm.h" 30 31 /* Tegra SDHOST controller vendor register definitions */ 32 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 33 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 34 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 35 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 36 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 37 38 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 39 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 40 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 41 #define NVQUIRK_DISABLE_SDR50 BIT(3) 42 #define NVQUIRK_DISABLE_SDR104 BIT(4) 43 #define NVQUIRK_DISABLE_DDR50 BIT(5) 44 45 struct sdhci_tegra_soc_data { 46 const struct sdhci_pltfm_data *pdata; 47 u32 nvquirks; 48 }; 49 50 struct sdhci_tegra { 51 const struct sdhci_tegra_soc_data *soc_data; 52 int power_gpio; 53 }; 54 55 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 56 { 57 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 58 struct sdhci_tegra *tegra_host = pltfm_host->priv; 59 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 60 61 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 62 (reg == SDHCI_HOST_VERSION))) { 63 /* Erratum: Version register is invalid in HW. */ 64 return SDHCI_SPEC_200; 65 } 66 67 return readw(host->ioaddr + reg); 68 } 69 70 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 71 { 72 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 73 74 switch (reg) { 75 case SDHCI_TRANSFER_MODE: 76 /* 77 * Postpone this write, we must do it together with a 78 * command write that is down below. 79 */ 80 pltfm_host->xfer_mode_shadow = val; 81 return; 82 case SDHCI_COMMAND: 83 writel((val << 16) | pltfm_host->xfer_mode_shadow, 84 host->ioaddr + SDHCI_TRANSFER_MODE); 85 return; 86 } 87 88 writew(val, host->ioaddr + reg); 89 } 90 91 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 92 { 93 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 94 struct sdhci_tegra *tegra_host = pltfm_host->priv; 95 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 96 97 /* Seems like we're getting spurious timeout and crc errors, so 98 * disable signalling of them. In case of real errors software 99 * timers should take care of eventually detecting them. 100 */ 101 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 102 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 103 104 writel(val, host->ioaddr + reg); 105 106 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 107 (reg == SDHCI_INT_ENABLE))) { 108 /* Erratum: Must enable block gap interrupt detection */ 109 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 110 if (val & SDHCI_INT_CARD_INT) 111 gap_ctrl |= 0x8; 112 else 113 gap_ctrl &= ~0x8; 114 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 115 } 116 } 117 118 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 119 { 120 return mmc_gpio_get_ro(host->mmc); 121 } 122 123 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 124 { 125 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 126 struct sdhci_tegra *tegra_host = pltfm_host->priv; 127 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 128 u32 misc_ctrl; 129 130 sdhci_reset(host, mask); 131 132 if (!(mask & SDHCI_RESET_ALL)) 133 return; 134 135 misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 136 /* Erratum: Enable SDHCI spec v3.00 support */ 137 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 138 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 139 /* Don't advertise UHS modes which aren't supported yet */ 140 if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50) 141 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50; 142 if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50) 143 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50; 144 if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104) 145 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104; 146 sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 147 } 148 149 static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) 150 { 151 u32 ctrl; 152 153 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 154 if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) && 155 (bus_width == MMC_BUS_WIDTH_8)) { 156 ctrl &= ~SDHCI_CTRL_4BITBUS; 157 ctrl |= SDHCI_CTRL_8BITBUS; 158 } else { 159 ctrl &= ~SDHCI_CTRL_8BITBUS; 160 if (bus_width == MMC_BUS_WIDTH_4) 161 ctrl |= SDHCI_CTRL_4BITBUS; 162 else 163 ctrl &= ~SDHCI_CTRL_4BITBUS; 164 } 165 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 166 } 167 168 static const struct sdhci_ops tegra_sdhci_ops = { 169 .get_ro = tegra_sdhci_get_ro, 170 .read_w = tegra_sdhci_readw, 171 .write_l = tegra_sdhci_writel, 172 .set_clock = sdhci_set_clock, 173 .set_bus_width = tegra_sdhci_set_bus_width, 174 .reset = tegra_sdhci_reset, 175 .set_uhs_signaling = sdhci_set_uhs_signaling, 176 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 177 }; 178 179 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 180 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 181 SDHCI_QUIRK_SINGLE_POWER_WRITE | 182 SDHCI_QUIRK_NO_HISPD_BIT | 183 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 184 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 185 .ops = &tegra_sdhci_ops, 186 }; 187 188 static struct sdhci_tegra_soc_data soc_data_tegra20 = { 189 .pdata = &sdhci_tegra20_pdata, 190 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 191 NVQUIRK_ENABLE_BLOCK_GAP_DET, 192 }; 193 194 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 195 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 196 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 197 SDHCI_QUIRK_SINGLE_POWER_WRITE | 198 SDHCI_QUIRK_NO_HISPD_BIT | 199 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 200 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 201 .ops = &tegra_sdhci_ops, 202 }; 203 204 static struct sdhci_tegra_soc_data soc_data_tegra30 = { 205 .pdata = &sdhci_tegra30_pdata, 206 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 207 NVQUIRK_DISABLE_SDR50 | 208 NVQUIRK_DISABLE_SDR104, 209 }; 210 211 static const struct sdhci_ops tegra114_sdhci_ops = { 212 .get_ro = tegra_sdhci_get_ro, 213 .read_w = tegra_sdhci_readw, 214 .write_w = tegra_sdhci_writew, 215 .write_l = tegra_sdhci_writel, 216 .set_clock = sdhci_set_clock, 217 .set_bus_width = tegra_sdhci_set_bus_width, 218 .reset = tegra_sdhci_reset, 219 .set_uhs_signaling = sdhci_set_uhs_signaling, 220 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 221 }; 222 223 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 224 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 225 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 226 SDHCI_QUIRK_SINGLE_POWER_WRITE | 227 SDHCI_QUIRK_NO_HISPD_BIT | 228 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 229 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 230 .ops = &tegra114_sdhci_ops, 231 }; 232 233 static struct sdhci_tegra_soc_data soc_data_tegra114 = { 234 .pdata = &sdhci_tegra114_pdata, 235 .nvquirks = NVQUIRK_DISABLE_SDR50 | 236 NVQUIRK_DISABLE_DDR50 | 237 NVQUIRK_DISABLE_SDR104, 238 }; 239 240 static const struct of_device_id sdhci_tegra_dt_match[] = { 241 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 }, 242 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 243 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 244 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 245 {} 246 }; 247 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 248 249 static int sdhci_tegra_parse_dt(struct device *dev) 250 { 251 struct device_node *np = dev->of_node; 252 struct sdhci_host *host = dev_get_drvdata(dev); 253 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 254 struct sdhci_tegra *tegra_host = pltfm_host->priv; 255 256 tegra_host->power_gpio = of_get_named_gpio(np, "power-gpios", 0); 257 return mmc_of_parse(host->mmc); 258 } 259 260 static int sdhci_tegra_probe(struct platform_device *pdev) 261 { 262 const struct of_device_id *match; 263 const struct sdhci_tegra_soc_data *soc_data; 264 struct sdhci_host *host; 265 struct sdhci_pltfm_host *pltfm_host; 266 struct sdhci_tegra *tegra_host; 267 struct clk *clk; 268 int rc; 269 270 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 271 if (!match) 272 return -EINVAL; 273 soc_data = match->data; 274 275 host = sdhci_pltfm_init(pdev, soc_data->pdata, 0); 276 if (IS_ERR(host)) 277 return PTR_ERR(host); 278 pltfm_host = sdhci_priv(host); 279 280 tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL); 281 if (!tegra_host) { 282 dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n"); 283 rc = -ENOMEM; 284 goto err_alloc_tegra_host; 285 } 286 tegra_host->soc_data = soc_data; 287 pltfm_host->priv = tegra_host; 288 289 rc = sdhci_tegra_parse_dt(&pdev->dev); 290 if (rc) 291 goto err_parse_dt; 292 293 if (gpio_is_valid(tegra_host->power_gpio)) { 294 rc = devm_gpio_request(&pdev->dev, tegra_host->power_gpio, 295 "sdhci_power"); 296 if (rc) { 297 dev_err(mmc_dev(host->mmc), 298 "failed to allocate power gpio\n"); 299 goto err_power_req; 300 } 301 gpio_direction_output(tegra_host->power_gpio, 1); 302 } 303 304 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 305 if (IS_ERR(clk)) { 306 dev_err(mmc_dev(host->mmc), "clk err\n"); 307 rc = PTR_ERR(clk); 308 goto err_clk_get; 309 } 310 clk_prepare_enable(clk); 311 pltfm_host->clk = clk; 312 313 rc = sdhci_add_host(host); 314 if (rc) 315 goto err_add_host; 316 317 return 0; 318 319 err_add_host: 320 clk_disable_unprepare(pltfm_host->clk); 321 err_clk_get: 322 err_power_req: 323 err_parse_dt: 324 err_alloc_tegra_host: 325 sdhci_pltfm_free(pdev); 326 return rc; 327 } 328 329 static struct platform_driver sdhci_tegra_driver = { 330 .driver = { 331 .name = "sdhci-tegra", 332 .of_match_table = sdhci_tegra_dt_match, 333 .pm = SDHCI_PLTFM_PMOPS, 334 }, 335 .probe = sdhci_tegra_probe, 336 .remove = sdhci_pltfm_unregister, 337 }; 338 339 module_platform_driver(sdhci_tegra_driver); 340 341 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 342 MODULE_AUTHOR("Google, Inc."); 343 MODULE_LICENSE("GPL v2"); 344