1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/clk.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/mmc/card.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/mmc.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/gpio/consumer.h> 29 30 #include "sdhci-pltfm.h" 31 32 /* Tegra SDHOST controller vendor register definitions */ 33 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100 34 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000 35 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16 36 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5) 37 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3) 38 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2) 39 40 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 41 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 42 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 43 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 44 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 45 46 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 47 #define SDHCI_AUTO_CAL_START BIT(31) 48 #define SDHCI_AUTO_CAL_ENABLE BIT(29) 49 50 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 51 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 52 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 53 #define NVQUIRK_ENABLE_SDR50 BIT(3) 54 #define NVQUIRK_ENABLE_SDR104 BIT(4) 55 #define NVQUIRK_ENABLE_DDR50 BIT(5) 56 #define NVQUIRK_HAS_PADCALIB BIT(6) 57 58 struct sdhci_tegra_soc_data { 59 const struct sdhci_pltfm_data *pdata; 60 u32 nvquirks; 61 }; 62 63 struct sdhci_tegra { 64 const struct sdhci_tegra_soc_data *soc_data; 65 struct gpio_desc *power_gpio; 66 bool ddr_signaling; 67 bool pad_calib_required; 68 }; 69 70 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 71 { 72 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 73 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 74 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 75 76 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 77 (reg == SDHCI_HOST_VERSION))) { 78 /* Erratum: Version register is invalid in HW. */ 79 return SDHCI_SPEC_200; 80 } 81 82 return readw(host->ioaddr + reg); 83 } 84 85 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 86 { 87 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 88 89 switch (reg) { 90 case SDHCI_TRANSFER_MODE: 91 /* 92 * Postpone this write, we must do it together with a 93 * command write that is down below. 94 */ 95 pltfm_host->xfer_mode_shadow = val; 96 return; 97 case SDHCI_COMMAND: 98 writel((val << 16) | pltfm_host->xfer_mode_shadow, 99 host->ioaddr + SDHCI_TRANSFER_MODE); 100 return; 101 } 102 103 writew(val, host->ioaddr + reg); 104 } 105 106 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 107 { 108 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 109 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 110 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 111 112 /* Seems like we're getting spurious timeout and crc errors, so 113 * disable signalling of them. In case of real errors software 114 * timers should take care of eventually detecting them. 115 */ 116 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 117 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 118 119 writel(val, host->ioaddr + reg); 120 121 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 122 (reg == SDHCI_INT_ENABLE))) { 123 /* Erratum: Must enable block gap interrupt detection */ 124 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 125 if (val & SDHCI_INT_CARD_INT) 126 gap_ctrl |= 0x8; 127 else 128 gap_ctrl &= ~0x8; 129 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 130 } 131 } 132 133 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 134 { 135 return mmc_gpio_get_ro(host->mmc); 136 } 137 138 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 139 { 140 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 141 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 142 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 143 u32 misc_ctrl, clk_ctrl; 144 145 sdhci_reset(host, mask); 146 147 if (!(mask & SDHCI_RESET_ALL)) 148 return; 149 150 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 151 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 152 153 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 | 154 SDHCI_MISC_CTRL_ENABLE_SDR50 | 155 SDHCI_MISC_CTRL_ENABLE_DDR50 | 156 SDHCI_MISC_CTRL_ENABLE_SDR104); 157 158 clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE; 159 160 /* 161 * If the board does not define a regulator for the SDHCI 162 * IO voltage, then don't advertise support for UHS modes 163 * even if the device supports it because the IO voltage 164 * cannot be configured. 165 */ 166 if (!IS_ERR(host->mmc->supply.vqmmc)) { 167 /* Erratum: Enable SDHCI spec v3.00 support */ 168 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 169 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 170 /* Advertise UHS modes as supported by host */ 171 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) 172 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50; 173 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 174 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50; 175 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) 176 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104; 177 if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50) 178 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; 179 } 180 181 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 182 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 183 184 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 185 tegra_host->pad_calib_required = true; 186 187 tegra_host->ddr_signaling = false; 188 } 189 190 static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) 191 { 192 u32 ctrl; 193 194 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 195 if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) && 196 (bus_width == MMC_BUS_WIDTH_8)) { 197 ctrl &= ~SDHCI_CTRL_4BITBUS; 198 ctrl |= SDHCI_CTRL_8BITBUS; 199 } else { 200 ctrl &= ~SDHCI_CTRL_8BITBUS; 201 if (bus_width == MMC_BUS_WIDTH_4) 202 ctrl |= SDHCI_CTRL_4BITBUS; 203 else 204 ctrl &= ~SDHCI_CTRL_4BITBUS; 205 } 206 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 207 } 208 209 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) 210 { 211 u32 val; 212 213 mdelay(1); 214 215 val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); 216 val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; 217 sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG); 218 } 219 220 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 221 { 222 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 223 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 224 unsigned long host_clk; 225 226 if (!clock) 227 return sdhci_set_clock(host, clock); 228 229 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 230 clk_set_rate(pltfm_host->clk, host_clk); 231 host->max_clk = clk_get_rate(pltfm_host->clk); 232 233 sdhci_set_clock(host, clock); 234 235 if (tegra_host->pad_calib_required) { 236 tegra_sdhci_pad_autocalib(host); 237 tegra_host->pad_calib_required = false; 238 } 239 } 240 241 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 242 unsigned timing) 243 { 244 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 245 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 246 247 if (timing == MMC_TIMING_UHS_DDR50) 248 tegra_host->ddr_signaling = true; 249 250 return sdhci_set_uhs_signaling(host, timing); 251 } 252 253 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 254 { 255 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 256 257 /* 258 * DDR modes require the host to run at double the card frequency, so 259 * the maximum rate we can support is half of the module input clock. 260 */ 261 return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2; 262 } 263 264 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) 265 { 266 u32 reg; 267 268 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 269 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; 270 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; 271 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); 272 } 273 274 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 275 { 276 unsigned int min, max; 277 278 /* 279 * Start search for minimum tap value at 10, as smaller values are 280 * may wrongly be reported as working but fail at higher speeds, 281 * according to the TRM. 282 */ 283 min = 10; 284 while (min < 255) { 285 tegra_sdhci_set_tap(host, min); 286 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 287 break; 288 min++; 289 } 290 291 /* Find the maximum tap value that still passes. */ 292 max = min + 1; 293 while (max < 255) { 294 tegra_sdhci_set_tap(host, max); 295 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 296 max--; 297 break; 298 } 299 max++; 300 } 301 302 /* The TRM states the ideal tap value is at 75% in the passing range. */ 303 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); 304 305 return mmc_send_tuning(host->mmc, opcode, NULL); 306 } 307 308 static void tegra_sdhci_voltage_switch(struct sdhci_host *host) 309 { 310 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 311 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); 312 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 313 314 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) 315 tegra_host->pad_calib_required = true; 316 } 317 318 static const struct sdhci_ops tegra_sdhci_ops = { 319 .get_ro = tegra_sdhci_get_ro, 320 .read_w = tegra_sdhci_readw, 321 .write_l = tegra_sdhci_writel, 322 .set_clock = tegra_sdhci_set_clock, 323 .set_bus_width = tegra_sdhci_set_bus_width, 324 .reset = tegra_sdhci_reset, 325 .platform_execute_tuning = tegra_sdhci_execute_tuning, 326 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 327 .voltage_switch = tegra_sdhci_voltage_switch, 328 .get_max_clock = tegra_sdhci_get_max_clock, 329 }; 330 331 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 332 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 333 SDHCI_QUIRK_SINGLE_POWER_WRITE | 334 SDHCI_QUIRK_NO_HISPD_BIT | 335 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 336 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 337 .ops = &tegra_sdhci_ops, 338 }; 339 340 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 341 .pdata = &sdhci_tegra20_pdata, 342 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 343 NVQUIRK_ENABLE_BLOCK_GAP_DET, 344 }; 345 346 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 347 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 348 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 349 SDHCI_QUIRK_SINGLE_POWER_WRITE | 350 SDHCI_QUIRK_NO_HISPD_BIT | 351 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 352 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 353 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 354 .ops = &tegra_sdhci_ops, 355 }; 356 357 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 358 .pdata = &sdhci_tegra30_pdata, 359 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 360 NVQUIRK_ENABLE_SDR50 | 361 NVQUIRK_ENABLE_SDR104 | 362 NVQUIRK_HAS_PADCALIB, 363 }; 364 365 static const struct sdhci_ops tegra114_sdhci_ops = { 366 .get_ro = tegra_sdhci_get_ro, 367 .read_w = tegra_sdhci_readw, 368 .write_w = tegra_sdhci_writew, 369 .write_l = tegra_sdhci_writel, 370 .set_clock = tegra_sdhci_set_clock, 371 .set_bus_width = tegra_sdhci_set_bus_width, 372 .reset = tegra_sdhci_reset, 373 .platform_execute_tuning = tegra_sdhci_execute_tuning, 374 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 375 .voltage_switch = tegra_sdhci_voltage_switch, 376 .get_max_clock = tegra_sdhci_get_max_clock, 377 }; 378 379 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 380 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 381 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 382 SDHCI_QUIRK_SINGLE_POWER_WRITE | 383 SDHCI_QUIRK_NO_HISPD_BIT | 384 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 385 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 386 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 387 .ops = &tegra114_sdhci_ops, 388 }; 389 390 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 391 .pdata = &sdhci_tegra114_pdata, 392 }; 393 394 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 395 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 396 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 397 SDHCI_QUIRK_SINGLE_POWER_WRITE | 398 SDHCI_QUIRK_NO_HISPD_BIT | 399 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 400 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 401 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 402 .ops = &tegra114_sdhci_ops, 403 }; 404 405 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 406 .pdata = &sdhci_tegra210_pdata, 407 }; 408 409 static const struct of_device_id sdhci_tegra_dt_match[] = { 410 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 411 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 }, 412 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 413 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 414 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 415 {} 416 }; 417 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 418 419 static int sdhci_tegra_probe(struct platform_device *pdev) 420 { 421 const struct of_device_id *match; 422 const struct sdhci_tegra_soc_data *soc_data; 423 struct sdhci_host *host; 424 struct sdhci_pltfm_host *pltfm_host; 425 struct sdhci_tegra *tegra_host; 426 struct clk *clk; 427 int rc; 428 429 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 430 if (!match) 431 return -EINVAL; 432 soc_data = match->data; 433 434 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); 435 if (IS_ERR(host)) 436 return PTR_ERR(host); 437 pltfm_host = sdhci_priv(host); 438 439 tegra_host = sdhci_pltfm_priv(pltfm_host); 440 tegra_host->ddr_signaling = false; 441 tegra_host->pad_calib_required = false; 442 tegra_host->soc_data = soc_data; 443 444 rc = mmc_of_parse(host->mmc); 445 if (rc) 446 goto err_parse_dt; 447 448 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) 449 host->mmc->caps |= MMC_CAP_1_8V_DDR; 450 451 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 452 GPIOD_OUT_HIGH); 453 if (IS_ERR(tegra_host->power_gpio)) { 454 rc = PTR_ERR(tegra_host->power_gpio); 455 goto err_power_req; 456 } 457 458 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 459 if (IS_ERR(clk)) { 460 dev_err(mmc_dev(host->mmc), "clk err\n"); 461 rc = PTR_ERR(clk); 462 goto err_clk_get; 463 } 464 clk_prepare_enable(clk); 465 pltfm_host->clk = clk; 466 467 rc = sdhci_add_host(host); 468 if (rc) 469 goto err_add_host; 470 471 return 0; 472 473 err_add_host: 474 clk_disable_unprepare(pltfm_host->clk); 475 err_clk_get: 476 err_power_req: 477 err_parse_dt: 478 sdhci_pltfm_free(pdev); 479 return rc; 480 } 481 482 static struct platform_driver sdhci_tegra_driver = { 483 .driver = { 484 .name = "sdhci-tegra", 485 .of_match_table = sdhci_tegra_dt_match, 486 .pm = SDHCI_PLTFM_PMOPS, 487 }, 488 .probe = sdhci_tegra_probe, 489 .remove = sdhci_pltfm_unregister, 490 }; 491 492 module_platform_driver(sdhci_tegra_driver); 493 494 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 495 MODULE_AUTHOR("Google, Inc."); 496 MODULE_LICENSE("GPL v2"); 497