1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/err.h> 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/clk.h> 20 #include <linux/io.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/mmc/card.h> 24 #include <linux/mmc/host.h> 25 #include <linux/mmc/slot-gpio.h> 26 #include <linux/gpio/consumer.h> 27 28 #include "sdhci-pltfm.h" 29 30 /* Tegra SDHOST controller vendor register definitions */ 31 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 32 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 33 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 34 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 35 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 36 37 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) 38 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) 39 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) 40 #define NVQUIRK_DISABLE_SDR50 BIT(3) 41 #define NVQUIRK_DISABLE_SDR104 BIT(4) 42 #define NVQUIRK_DISABLE_DDR50 BIT(5) 43 44 struct sdhci_tegra_soc_data { 45 const struct sdhci_pltfm_data *pdata; 46 u32 nvquirks; 47 }; 48 49 struct sdhci_tegra { 50 const struct sdhci_tegra_soc_data *soc_data; 51 struct gpio_desc *power_gpio; 52 bool ddr_signaling; 53 }; 54 55 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) 56 { 57 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 58 struct sdhci_tegra *tegra_host = pltfm_host->priv; 59 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 60 61 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && 62 (reg == SDHCI_HOST_VERSION))) { 63 /* Erratum: Version register is invalid in HW. */ 64 return SDHCI_SPEC_200; 65 } 66 67 return readw(host->ioaddr + reg); 68 } 69 70 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 71 { 72 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 73 74 switch (reg) { 75 case SDHCI_TRANSFER_MODE: 76 /* 77 * Postpone this write, we must do it together with a 78 * command write that is down below. 79 */ 80 pltfm_host->xfer_mode_shadow = val; 81 return; 82 case SDHCI_COMMAND: 83 writel((val << 16) | pltfm_host->xfer_mode_shadow, 84 host->ioaddr + SDHCI_TRANSFER_MODE); 85 return; 86 } 87 88 writew(val, host->ioaddr + reg); 89 } 90 91 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 92 { 93 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 94 struct sdhci_tegra *tegra_host = pltfm_host->priv; 95 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 96 97 /* Seems like we're getting spurious timeout and crc errors, so 98 * disable signalling of them. In case of real errors software 99 * timers should take care of eventually detecting them. 100 */ 101 if (unlikely(reg == SDHCI_SIGNAL_ENABLE)) 102 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC); 103 104 writel(val, host->ioaddr + reg); 105 106 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && 107 (reg == SDHCI_INT_ENABLE))) { 108 /* Erratum: Must enable block gap interrupt detection */ 109 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 110 if (val & SDHCI_INT_CARD_INT) 111 gap_ctrl |= 0x8; 112 else 113 gap_ctrl &= ~0x8; 114 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); 115 } 116 } 117 118 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host) 119 { 120 return mmc_gpio_get_ro(host->mmc); 121 } 122 123 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) 124 { 125 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 126 struct sdhci_tegra *tegra_host = pltfm_host->priv; 127 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; 128 u32 misc_ctrl; 129 130 sdhci_reset(host, mask); 131 132 if (!(mask & SDHCI_RESET_ALL)) 133 return; 134 135 misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); 136 /* Erratum: Enable SDHCI spec v3.00 support */ 137 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) 138 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; 139 /* Don't advertise UHS modes which aren't supported yet */ 140 if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50) 141 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50; 142 if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50) 143 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50; 144 if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104) 145 misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104; 146 sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); 147 148 tegra_host->ddr_signaling = false; 149 } 150 151 static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) 152 { 153 u32 ctrl; 154 155 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 156 if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) && 157 (bus_width == MMC_BUS_WIDTH_8)) { 158 ctrl &= ~SDHCI_CTRL_4BITBUS; 159 ctrl |= SDHCI_CTRL_8BITBUS; 160 } else { 161 ctrl &= ~SDHCI_CTRL_8BITBUS; 162 if (bus_width == MMC_BUS_WIDTH_4) 163 ctrl |= SDHCI_CTRL_4BITBUS; 164 else 165 ctrl &= ~SDHCI_CTRL_4BITBUS; 166 } 167 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 168 } 169 170 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 171 { 172 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 173 struct sdhci_tegra *tegra_host = pltfm_host->priv; 174 unsigned long host_clk; 175 176 if (!clock) 177 return; 178 179 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; 180 clk_set_rate(pltfm_host->clk, host_clk); 181 host->max_clk = clk_get_rate(pltfm_host->clk); 182 183 return sdhci_set_clock(host, clock); 184 } 185 186 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, 187 unsigned timing) 188 { 189 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 190 struct sdhci_tegra *tegra_host = pltfm_host->priv; 191 192 if (timing == MMC_TIMING_UHS_DDR50) 193 tegra_host->ddr_signaling = true; 194 195 return sdhci_set_uhs_signaling(host, timing); 196 } 197 198 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) 199 { 200 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 201 202 /* 203 * DDR modes require the host to run at double the card frequency, so 204 * the maximum rate we can support is half of the module input clock. 205 */ 206 return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2; 207 } 208 209 static const struct sdhci_ops tegra_sdhci_ops = { 210 .get_ro = tegra_sdhci_get_ro, 211 .read_w = tegra_sdhci_readw, 212 .write_l = tegra_sdhci_writel, 213 .set_clock = tegra_sdhci_set_clock, 214 .set_bus_width = tegra_sdhci_set_bus_width, 215 .reset = tegra_sdhci_reset, 216 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 217 .get_max_clock = tegra_sdhci_get_max_clock, 218 }; 219 220 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { 221 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 222 SDHCI_QUIRK_SINGLE_POWER_WRITE | 223 SDHCI_QUIRK_NO_HISPD_BIT | 224 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 225 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 226 .ops = &tegra_sdhci_ops, 227 }; 228 229 static const struct sdhci_tegra_soc_data soc_data_tegra20 = { 230 .pdata = &sdhci_tegra20_pdata, 231 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 | 232 NVQUIRK_ENABLE_BLOCK_GAP_DET, 233 }; 234 235 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { 236 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 237 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 238 SDHCI_QUIRK_SINGLE_POWER_WRITE | 239 SDHCI_QUIRK_NO_HISPD_BIT | 240 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 241 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 242 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 243 .ops = &tegra_sdhci_ops, 244 }; 245 246 static const struct sdhci_tegra_soc_data soc_data_tegra30 = { 247 .pdata = &sdhci_tegra30_pdata, 248 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | 249 NVQUIRK_DISABLE_SDR50 | 250 NVQUIRK_DISABLE_SDR104, 251 }; 252 253 static const struct sdhci_ops tegra114_sdhci_ops = { 254 .get_ro = tegra_sdhci_get_ro, 255 .read_w = tegra_sdhci_readw, 256 .write_w = tegra_sdhci_writew, 257 .write_l = tegra_sdhci_writel, 258 .set_clock = tegra_sdhci_set_clock, 259 .set_bus_width = tegra_sdhci_set_bus_width, 260 .reset = tegra_sdhci_reset, 261 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling, 262 .get_max_clock = tegra_sdhci_get_max_clock, 263 }; 264 265 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { 266 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 267 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 268 SDHCI_QUIRK_SINGLE_POWER_WRITE | 269 SDHCI_QUIRK_NO_HISPD_BIT | 270 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 271 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 272 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 273 .ops = &tegra114_sdhci_ops, 274 }; 275 276 static const struct sdhci_tegra_soc_data soc_data_tegra114 = { 277 .pdata = &sdhci_tegra114_pdata, 278 .nvquirks = NVQUIRK_DISABLE_SDR50 | 279 NVQUIRK_DISABLE_DDR50 | 280 NVQUIRK_DISABLE_SDR104, 281 }; 282 283 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { 284 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 285 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 286 SDHCI_QUIRK_SINGLE_POWER_WRITE | 287 SDHCI_QUIRK_NO_HISPD_BIT | 288 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | 289 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 290 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 291 .ops = &tegra114_sdhci_ops, 292 }; 293 294 static const struct sdhci_tegra_soc_data soc_data_tegra210 = { 295 .pdata = &sdhci_tegra210_pdata, 296 .nvquirks = NVQUIRK_DISABLE_SDR50 | 297 NVQUIRK_DISABLE_DDR50 | 298 NVQUIRK_DISABLE_SDR104, 299 }; 300 301 static const struct of_device_id sdhci_tegra_dt_match[] = { 302 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, 303 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 }, 304 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 }, 305 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 }, 306 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 }, 307 {} 308 }; 309 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match); 310 311 static int sdhci_tegra_probe(struct platform_device *pdev) 312 { 313 const struct of_device_id *match; 314 const struct sdhci_tegra_soc_data *soc_data; 315 struct sdhci_host *host; 316 struct sdhci_pltfm_host *pltfm_host; 317 struct sdhci_tegra *tegra_host; 318 struct clk *clk; 319 int rc; 320 321 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); 322 if (!match) 323 return -EINVAL; 324 soc_data = match->data; 325 326 host = sdhci_pltfm_init(pdev, soc_data->pdata, 0); 327 if (IS_ERR(host)) 328 return PTR_ERR(host); 329 pltfm_host = sdhci_priv(host); 330 331 tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL); 332 if (!tegra_host) { 333 dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n"); 334 rc = -ENOMEM; 335 goto err_alloc_tegra_host; 336 } 337 tegra_host->ddr_signaling = false; 338 tegra_host->soc_data = soc_data; 339 pltfm_host->priv = tegra_host; 340 341 rc = mmc_of_parse(host->mmc); 342 if (rc) 343 goto err_parse_dt; 344 345 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", 346 GPIOD_OUT_HIGH); 347 if (IS_ERR(tegra_host->power_gpio)) { 348 rc = PTR_ERR(tegra_host->power_gpio); 349 goto err_power_req; 350 } 351 352 clk = devm_clk_get(mmc_dev(host->mmc), NULL); 353 if (IS_ERR(clk)) { 354 dev_err(mmc_dev(host->mmc), "clk err\n"); 355 rc = PTR_ERR(clk); 356 goto err_clk_get; 357 } 358 clk_prepare_enable(clk); 359 pltfm_host->clk = clk; 360 361 rc = sdhci_add_host(host); 362 if (rc) 363 goto err_add_host; 364 365 return 0; 366 367 err_add_host: 368 clk_disable_unprepare(pltfm_host->clk); 369 err_clk_get: 370 err_power_req: 371 err_parse_dt: 372 err_alloc_tegra_host: 373 sdhci_pltfm_free(pdev); 374 return rc; 375 } 376 377 static struct platform_driver sdhci_tegra_driver = { 378 .driver = { 379 .name = "sdhci-tegra", 380 .of_match_table = sdhci_tegra_dt_match, 381 .pm = SDHCI_PLTFM_PMOPS, 382 }, 383 .probe = sdhci_tegra_probe, 384 .remove = sdhci_pltfm_unregister, 385 }; 386 387 module_platform_driver(sdhci_tegra_driver); 388 389 MODULE_DESCRIPTION("SDHCI driver for Tegra"); 390 MODULE_AUTHOR("Google, Inc."); 391 MODULE_LICENSE("GPL v2"); 392