#
252425cb |
| 16-Dec-2020 |
Takeshi Saito <takeshi.saito.xv@renesas.com> |
mmc: renesas_sdhi_internal_dmac: Fix DMA buffer alignment from 8 to 128-bytes [ Upstream commit d7aefb2887601cf1fc3f86f55d43b2c9aece5e8f ] According to the latest datasheet, the int
mmc: renesas_sdhi_internal_dmac: Fix DMA buffer alignment from 8 to 128-bytes [ Upstream commit d7aefb2887601cf1fc3f86f55d43b2c9aece5e8f ] According to the latest datasheet, the internal DMAC buffer alignment R-Car Gen3 SDHI HW should be 128-bytes. So, fix it. Signed-off-by: Takeshi Saito <takeshi.saito.xv@renesas.com> [shimoda: revise commit description, rebase] Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/1608114572-1892-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7 |
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#
7320915c |
| 03-Sep-2020 |
Douglas Anderson <dianders@chromium.org> |
mmc: Set PROBE_PREFER_ASYNCHRONOUS for drivers that existed in v4.14 This is like commit 3d3451124f3d ("mmc: sdhci-msm: Prefer asynchronous probe") but applied to a whole pile of drivers
mmc: Set PROBE_PREFER_ASYNCHRONOUS for drivers that existed in v4.14 This is like commit 3d3451124f3d ("mmc: sdhci-msm: Prefer asynchronous probe") but applied to a whole pile of drivers. This batch converts the drivers that appeared to be around in the v4.14 timeframe. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # SDHI drivers Link: https://lore.kernel.org/r/20200903162412.3.Id1ff21470f08f427aedd0a6535dcd83ccc56b278@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
55118e53 |
| 03-Sep-2020 |
Robin Murphy <robin.murphy@arm.com> |
mmc: renesas_sdhi: Drop local dma_parms Since commit 9495b7e92f71 ("driver core: platform: Initialize dma_parms for platform devices"), struct platform_device already provides a dma_
mmc: renesas_sdhi: Drop local dma_parms Since commit 9495b7e92f71 ("driver core: platform: Initialize dma_parms for platform devices"), struct platform_device already provides a dma_parms structure, so we can save allocating another one. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/85e1fc97dbec3dea96102785a5e308ccb5e91cfe.1599167798.git.robin.murphy@arm.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43 |
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#
58a91d96 |
| 21-May-2020 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
mmc: renesas_sdhi_internal_dmac: Fix dma unmapping in error cases If this controller doesn't issue interrupt for response of command, this driver lacks to call dma_unmap_sg(). So, fix th
mmc: renesas_sdhi_internal_dmac: Fix dma unmapping in error cases If this controller doesn't issue interrupt for response of command, this driver lacks to call dma_unmap_sg(). So, fix the issue by using end() of struct tmio_mmc_dma_ops. Reported-by: Takeshi Saito <takeshi.saito.xv@renesas.com> Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1590044466-28372-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
2b26e34e |
| 21-May-2020 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
mmc: renesas_sdhi_internal_dmac: clean up the code for dma complete To add end() operation in the future, clean the code of renesas_sdhi_internal_dmac_complete_tasklet_fn(). No behavior
mmc: renesas_sdhi_internal_dmac: clean up the code for dma complete To add end() operation in the future, clean the code of renesas_sdhi_internal_dmac_complete_tasklet_fn(). No behavior change. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1590044466-28372-3-git-send-email-yoshihiro.shimoda.uh@renesas.com Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2 |
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#
c1a49782 |
| 03-Dec-2019 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
mmc: renesas_sdhi: use recent tap values for HS400 New datasheets require different and new values for HS400 with 4taps or 8taps. Signed-off-by: Wolfram Sang <wsa+renesas@sang-e
mmc: renesas_sdhi: use recent tap values for HS400 New datasheets require different and new values for HS400 with 4taps or 8taps. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191203200513.1758-6-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
a0fb3fc8 |
| 03-Dec-2019 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
mmc: renesas_sdhi: remove whitelist for internal DMAC We know now that there won't be Gen3 SoCs with both, SYS-DMAC and internal DMAC. We removed the blacklisting for SYS-DMAC already, s
mmc: renesas_sdhi: remove whitelist for internal DMAC We know now that there won't be Gen3 SoCs with both, SYS-DMAC and internal DMAC. We removed the blacklisting for SYS-DMAC already, so we can remove the whitelisting for internal DMAC, too. This makes adding new SoCs easier. We keep the quirk handling, of course. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191203194859.917-1-wsa@the-dreams.de Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2 |
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c9af138c |
| 24-Sep-2019 |
Biju Das <biju.das@bp.renesas.com> |
mmc: renesas_sdhi_internal_dmac: Add r8a774b1 support This patch adds SDHI support for RZ/G2N (R8A774B1) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Wolf
mmc: renesas_sdhi_internal_dmac: Add r8a774b1 support This patch adds SDHI support for RZ/G2N (R8A774B1) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.3.1, v5.3 |
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#
c7d9eccb |
| 11-Sep-2019 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
mmc: renesas_sdhi_internal_dmac: Add MMC_CAP2_MERGE_CAPABLE Since this host controller can merge bigger segments if DMA API layer cam merge the segments, this patch adds the flag.
mmc: renesas_sdhi_internal_dmac: Add MMC_CAP2_MERGE_CAPABLE Since this host controller can merge bigger segments if DMA API layer cam merge the segments, this patch adds the flag. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
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Revision tags: v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3 |
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#
2a55c1ea |
| 14-Mar-2019 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
mmc: renesas_sdhi: prevent overflow for max_req_size max_req_size is calculated by 'max_blk_size * max_blk_count' in the TMIO core. So, specifying U32_MAX as max_blk_count will overflow
mmc: renesas_sdhi: prevent overflow for max_req_size max_req_size is calculated by 'max_blk_size * max_blk_count' in the TMIO core. So, specifying U32_MAX as max_blk_count will overflow this calculation. It will cause no harm in practice because the immense high number will overflow into another immense high number. However, it is not good coding practice, so calculate max_blk_count so that max_req_size will fit into unsigned int on ARM32/64. Thanks to the Renesas BSP team for the bug report! Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
f49bdcde |
| 14-Mar-2019 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
mmc: renesas_sdhi: update copyright information Mostly year updates, but one addition as well. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon
mmc: renesas_sdhi: update copyright information Mostly year updates, but one addition as well. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund@ragnatech.se> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21 |
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f0c8234c |
| 08-Feb-2019 |
Takeshi Saito <takeshi.saito.xv@renesas.com> |
mmc: renesas_sdhi: Change HW adjustment register according to speed mode SCC is used for SDR104/HS200/HS400. We need to change SCC_DT2FF according to the mode. If it is inappropriate, CR
mmc: renesas_sdhi: Change HW adjustment register according to speed mode SCC is used for SDR104/HS200/HS400. We need to change SCC_DT2FF according to the mode. If it is inappropriate, CRC error tends to occur. This adds variable "tap_hs400" for HS400 mode and configures SCC_DT2FF as needed. Signed-off-by: Takeshi Saito <takeshi.saito.xv@renesas.com> [wsa: rebased to upstream and updated commit message] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund@ragnatech.se> Tested-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16, v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10 |
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#
ca804a56 |
| 13-Dec-2018 |
Biju Das <biju.das@bp.renesas.com> |
mmc: renesas_sdhi_internal_dmac: Whitelist r8a774c0 We need r8a774c0 to be whitelisted for SDHI to work on the RZ/G2E, but we don't care about the revision of the SoC, so just whitelist
mmc: renesas_sdhi_internal_dmac: Whitelist r8a774c0 We need r8a774c0 to be whitelisted for SDHI to work on the RZ/G2E, but we don't care about the revision of the SoC, so just whitelist the generic part number. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.19.9, v4.19.8, v4.19.7, v4.19.6 |
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#
2c907f05 |
| 28-Nov-2018 |
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> |
mmc: renesas_sdhi: align compatibility properties for H3 and M3-W It was though all ES revisions of H3 and M3-W SoCs required the TMIO_MMC_HAVE_4TAP_HS400 flag. Recent datasheet updates
mmc: renesas_sdhi: align compatibility properties for H3 and M3-W It was though all ES revisions of H3 and M3-W SoCs required the TMIO_MMC_HAVE_4TAP_HS400 flag. Recent datasheet updates tells us this is not true, only early ES revisions of the SoC do. Since quirk matching based on ES revisions is now used to handle the flag it's possible to align all Gen3 compatibility properties. This will allow later ES revisions of H3 and M3-W to use the correct 8-tap HS400 mode. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.19.5, v4.19.4, v4.18.20, v4.19.3, v4.18.19, v4.19.2, v4.18.18 |
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#
0204da24 |
| 05-Nov-2018 |
Marek Vasut <marek.vasut@gmail.com> |
mmc: renesas_sdhi: Whitelist R8A77990 SDHI Whitelist R8A77990 E3 SoC in the SDHI driver. The SDHI core present in the SoC is an 8tap variant of the Gen3 SDHI core. Signed-off-by
mmc: renesas_sdhi: Whitelist R8A77990 SDHI Whitelist R8A77990 E3 SoC in the SDHI driver. The SDHI core present in the SoC is an 8tap variant of the Gen3 SDHI core. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Simon Horman <horms+renesas@verge.net.au> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-renesas-soc@vger.kernel.org Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.18.17, v4.19.1 |
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#
9706b472 |
| 24-Oct-2018 |
Chris Brandt <chris.brandt@renesas.com> |
mmc: renesas_sdhi_internal_dmac: Add R7S9210 support The SDHI/MMC controller in the RZ/A2 is almost the same as R-Car gen3, but with some minor differences. Signed-off-by: Chris
mmc: renesas_sdhi_internal_dmac: Add R7S9210 support The SDHI/MMC controller in the RZ/A2 is almost the same as R-Car gen3, but with some minor differences. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.19, v4.18.16, v4.18.15, v4.18.14 |
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d3dd5db0 |
| 12-Oct-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
mmc: tmio: simplify the DMA mode test host->chan_{rx,tx} represents the DMA capability of the platform. Even if DMA is supported, there are cases where we want to use PIO, for exampl
mmc: tmio: simplify the DMA mode test host->chan_{rx,tx} represents the DMA capability of the platform. Even if DMA is supported, there are cases where we want to use PIO, for example, data length is short enough as commit 5f52c3552946 ("mmc: tmio: use PIO for short transfers") mentioned. Regarding the hardware control flow, we are interested in whether DMA is currently enabled or not, instead of whether the platform has the DMA capability. Hence, the several conditionals in tmio_mmc_core.c end up with checking host->chan_{rx,tx} and !host->force_pio. This is not nice. Let's flip the flag host->force_pio into host->dma_on. host->dma_on represents whether the DMA is currently enabled or not. This flag is set false in the beginning of each command, then should be set true by tmio_mmc_start_dma() when the DMA is turned on. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.18.13 |
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#
60ab43ba |
| 08-Oct-2018 |
Fabrizio Castro <fabrizio.castro@bp.renesas.com> |
mmc: renesas_sdhi: Add r8a77470 SDHI1 support The RZ/G1C (a.k.a. R8A77470) comes with three SDHI interfaces, SDHI0 and SDHI2 are compatible with the R-Car Gen2 SDHIs, SDHI1 is compat
mmc: renesas_sdhi: Add r8a77470 SDHI1 support The RZ/G1C (a.k.a. R8A77470) comes with three SDHI interfaces, SDHI0 and SDHI2 are compatible with the R-Car Gen2 SDHIs, SDHI1 is compatible with R-Car Gen3 SDHIs and it can be used as eMMC as well. This patch adds driver compatibility, and makes sure both drivers get compiled for the R8A77470. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.18.12, v4.18.11, v4.18.10, v4.18.9 |
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#
54541815 |
| 13-Sep-2018 |
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> |
mmc: renesas_sdhi_internal_dmac: set scatter/gather max segment size Fix warning when running with CONFIG_DMA_API_DEBUG_SG=y by allocating a device_dma_parameters structure and filling i
mmc: renesas_sdhi_internal_dmac: set scatter/gather max segment size Fix warning when running with CONFIG_DMA_API_DEBUG_SG=y by allocating a device_dma_parameters structure and filling in the max segment size. The size used is the result of a discussion with Renesas hardware engineers and unfortunately not found in the datasheet. renesas_sdhi_internal_dmac ee140000.sd: DMA-API: mapping sg segment longer than device claims to support [len=126976] [max=65536] Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> [wsa: simplified some logic after validating intended dma_parms life cycle and added comment] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4 |
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#
f707079d |
| 21-Aug-2018 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
mmc: use SPDX identifier for Renesas drivers Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf
mmc: use SPDX identifier for Renesas drivers Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
16a129b3 |
| 18-Aug-2018 |
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
mmc: renesas_sdhi_internal_dmac: add R8A77970 to whitelist I've successfully tested eMMC on the V3H Starter Kit board and since the R8A77970 SoC has a single SDHI core, it can't be a sub
mmc: renesas_sdhi_internal_dmac: add R8A77970 to whitelist I've successfully tested eMMC on the V3H Starter Kit board and since the R8A77970 SoC has a single SDHI core, it can't be a subject to the known RX DMA errata. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
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Revision tags: v4.18.3, v4.17.17 |
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c1ec8f86 |
| 17-Aug-2018 |
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
mmc: renesas_sdhi_internal_dmac: Fix a few typos Remove the stray underscore in the DM_CM_DTRAN_MODE.BUS_WIDTH register field name and fix the typo in the comment of the #define DTRA
mmc: renesas_sdhi_internal_dmac: Fix a few typos Remove the stray underscore in the DM_CM_DTRAN_MODE.BUS_WIDTH register field name and fix the typo in the comment of the #define DTRAN_MODE_CH_NUM_CH1. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v4.18.2, v4.17.16, v4.17.15, v4.18.1 |
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2e1501a8 |
| 14-Aug-2018 |
Fabrizio Castro <fabrizio.castro@bp.renesas.com> |
mmc: renesas_sdhi_internal_dmac: Whitelist r8a774a1 We need r8a774a1 to be whitelisted for SDHI to work on the RZ/G2M, but we don't care about the revision of the SoC, so just whitelist
mmc: renesas_sdhi_internal_dmac: Whitelist r8a774a1 We need r8a774a1 to be whitelisted for SDHI to work on the RZ/G2M, but we don't care about the revision of the SoC, so just whitelist the generic part number. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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d2332f88 |
| 22-Aug-2018 |
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
mmc: renesas_sdhi_internal_dmac: mask DMAC interrupts I have encountered an interrupt storm during the eMMC chip probing (and the chip finally didn't get detected). It turned out that U
mmc: renesas_sdhi_internal_dmac: mask DMAC interrupts I have encountered an interrupt storm during the eMMC chip probing (and the chip finally didn't get detected). It turned out that U-Boot left the SDHI DMA interrupts enabled while the Linux driver didn't use those. Masking those interrupts in renesas_sdhi_internal_dmac_request_dma() gets rid of both issues... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC") Cc: stable@vger.kernel.org # v4.14+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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9faf870e |
| 22-Aug-2018 |
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
mmc: renesas_sdhi_internal_dmac: fix #define RST_RESERVED_BITS The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits 32-63 defaulting to 0s -- fix off-by-one in #define
mmc: renesas_sdhi_internal_dmac: fix #define RST_RESERVED_BITS The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits 32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC") Cc: stable@vger.kernel.org # v4.14+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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