1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DMA support for Internal DMAC with SDHI SD/SDIO controller 4 * 5 * Copyright (C) 2016-17 Renesas Electronics Corporation 6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/io-64-nonatomic-hi-lo.h> 13 #include <linux/mfd/tmio.h> 14 #include <linux/mmc/host.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/pagemap.h> 18 #include <linux/scatterlist.h> 19 #include <linux/sys_soc.h> 20 21 #include "renesas_sdhi.h" 22 #include "tmio_mmc.h" 23 24 #define DM_CM_DTRAN_MODE 0x820 25 #define DM_CM_DTRAN_CTRL 0x828 26 #define DM_CM_RST 0x830 27 #define DM_CM_INFO1 0x840 28 #define DM_CM_INFO1_MASK 0x848 29 #define DM_CM_INFO2 0x850 30 #define DM_CM_INFO2_MASK 0x858 31 #define DM_DTRAN_ADDR 0x880 32 33 /* DM_CM_DTRAN_MODE */ 34 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 35 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */ 36 #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4)) 37 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */ 38 39 /* DM_CM_DTRAN_CTRL */ 40 #define DTRAN_CTRL_DM_START BIT(0) 41 42 /* DM_CM_RST */ 43 #define RST_DTRANRST1 BIT(9) 44 #define RST_DTRANRST0 BIT(8) 45 #define RST_RESERVED_BITS GENMASK_ULL(31, 0) 46 47 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 48 #define INFO1_CLEAR 0 49 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) 50 #define INFO1_DTRANEND1 BIT(17) 51 #define INFO1_DTRANEND0 BIT(16) 52 53 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 54 #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0) 55 #define INFO2_DTRANERR1 BIT(17) 56 #define INFO2_DTRANERR0 BIT(16) 57 58 /* 59 * Specification of this driver: 60 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 61 * - Since this SDHI DMAC register set has 16 but 32-bit width, we 62 * need a custom accessor. 63 */ 64 65 static unsigned long global_flags; 66 /* 67 * Workaround for avoiding to use RX DMAC by multiple channels. 68 * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use 69 * RX DMAC simultaneously, sometimes hundreds of bytes data are not 70 * stored into the system memory even if the DMAC interrupt happened. 71 * So, this driver then uses one RX DMAC channel only. 72 */ 73 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY 0 74 #define SDHI_INTERNAL_DMAC_RX_IN_USE 1 75 76 /* RZ/A2 does not have the ADRR_MODE bit */ 77 #define SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY 2 78 79 /* Definitions for sampling clocks */ 80 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 81 { 82 .clk_rate = 0, 83 .tap = 0x00000300, 84 }, 85 }; 86 87 static const struct renesas_sdhi_of_data of_rza2_compatible = { 88 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 89 TMIO_MMC_HAVE_CBSY, 90 .tmio_ocr_mask = MMC_VDD_32_33, 91 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 92 MMC_CAP_CMD23, 93 .bus_shift = 2, 94 .scc_offset = 0 - 0x1000, 95 .taps = rcar_gen3_scc_taps, 96 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 97 /* DMAC can handle 0xffffffff blk count but only 1 segment */ 98 .max_blk_count = 0xffffffff, 99 .max_segs = 1, 100 }; 101 102 static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = { 103 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 104 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 105 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 106 MMC_CAP_CMD23, 107 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT, 108 .bus_shift = 2, 109 .scc_offset = 0x1000, 110 .taps = rcar_gen3_scc_taps, 111 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 112 /* DMAC can handle 0xffffffff blk count but only 1 segment */ 113 .max_blk_count = 0xffffffff, 114 .max_segs = 1, 115 }; 116 117 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 118 { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, }, 119 { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, }, 120 { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, }, 121 { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, }, 122 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 123 {}, 124 }; 125 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 126 127 static void 128 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host, 129 int addr, u64 val) 130 { 131 writeq(val, host->ctl + addr); 132 } 133 134 static void 135 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 136 { 137 struct renesas_sdhi *priv = host_to_priv(host); 138 139 if (!host->chan_tx || !host->chan_rx) 140 return; 141 142 if (!enable) 143 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1, 144 INFO1_CLEAR); 145 146 if (priv->dma_priv.enable) 147 priv->dma_priv.enable(host, enable); 148 } 149 150 static void 151 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) { 152 u64 val = RST_DTRANRST1 | RST_DTRANRST0; 153 154 renesas_sdhi_internal_dmac_enable_dma(host, false); 155 156 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 157 RST_RESERVED_BITS & ~val); 158 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 159 RST_RESERVED_BITS | val); 160 161 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 162 163 renesas_sdhi_internal_dmac_enable_dma(host, true); 164 } 165 166 static void 167 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) { 168 struct renesas_sdhi *priv = host_to_priv(host); 169 170 tasklet_schedule(&priv->dma_priv.dma_complete); 171 } 172 173 static void 174 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 175 struct mmc_data *data) 176 { 177 struct scatterlist *sg = host->sg_ptr; 178 u32 dtran_mode = DTRAN_MODE_BUS_WIDTH; 179 180 if (!test_bit(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY, &global_flags)) 181 dtran_mode |= DTRAN_MODE_ADDR_MODE; 182 183 if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len, 184 mmc_get_dma_dir(data))) 185 goto force_pio; 186 187 /* This DMAC cannot handle if buffer is not 8-bytes alignment */ 188 if (!IS_ALIGNED(sg_dma_address(sg), 8)) 189 goto force_pio_with_unmap; 190 191 if (data->flags & MMC_DATA_READ) { 192 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 193 if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) && 194 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags)) 195 goto force_pio_with_unmap; 196 } else { 197 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 198 } 199 200 renesas_sdhi_internal_dmac_enable_dma(host, true); 201 202 /* set dma parameters */ 203 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE, 204 dtran_mode); 205 renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR, 206 sg_dma_address(sg)); 207 208 host->dma_on = true; 209 210 return; 211 212 force_pio_with_unmap: 213 dma_unmap_sg(&host->pdev->dev, sg, host->sg_len, mmc_get_dma_dir(data)); 214 215 force_pio: 216 renesas_sdhi_internal_dmac_enable_dma(host, false); 217 } 218 219 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 220 { 221 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 222 223 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 224 225 /* start the DMAC */ 226 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL, 227 DTRAN_CTRL_DM_START); 228 } 229 230 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) 231 { 232 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 233 enum dma_data_direction dir; 234 235 spin_lock_irq(&host->lock); 236 237 if (!host->data) 238 goto out; 239 240 if (host->data->flags & MMC_DATA_READ) 241 dir = DMA_FROM_DEVICE; 242 else 243 dir = DMA_TO_DEVICE; 244 245 renesas_sdhi_internal_dmac_enable_dma(host, false); 246 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir); 247 248 if (dir == DMA_FROM_DEVICE) 249 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 250 251 tmio_mmc_do_data_irq(host); 252 out: 253 spin_unlock_irq(&host->lock); 254 } 255 256 static void 257 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 258 struct tmio_mmc_data *pdata) 259 { 260 struct renesas_sdhi *priv = host_to_priv(host); 261 262 /* Disable DMAC interrupts, we don't use them */ 263 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK, 264 INFO1_MASK_CLEAR); 265 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK, 266 INFO2_MASK_CLEAR); 267 268 /* Each value is set to non-zero to assume "enabling" each DMA */ 269 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 270 271 tasklet_init(&priv->dma_priv.dma_complete, 272 renesas_sdhi_internal_dmac_complete_tasklet_fn, 273 (unsigned long)host); 274 tasklet_init(&host->dma_issue, 275 renesas_sdhi_internal_dmac_issue_tasklet_fn, 276 (unsigned long)host); 277 } 278 279 static void 280 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 281 { 282 /* Each value is set to zero to assume "disabling" each DMA */ 283 host->chan_rx = host->chan_tx = NULL; 284 } 285 286 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 287 .start = renesas_sdhi_internal_dmac_start_dma, 288 .enable = renesas_sdhi_internal_dmac_enable_dma, 289 .request = renesas_sdhi_internal_dmac_request_dma, 290 .release = renesas_sdhi_internal_dmac_release_dma, 291 .abort = renesas_sdhi_internal_dmac_abort_dma, 292 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 293 }; 294 295 /* 296 * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC 297 * implementation as others may use a different implementation. 298 */ 299 static const struct soc_device_attribute soc_whitelist[] = { 300 /* specific ones */ 301 { .soc_id = "r7s9210", 302 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY) }, 303 { .soc_id = "r8a7795", .revision = "ES1.*", 304 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 305 { .soc_id = "r8a7796", .revision = "ES1.0", 306 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 307 /* generic ones */ 308 { .soc_id = "r8a774a1" }, 309 { .soc_id = "r8a77470" }, 310 { .soc_id = "r8a7795" }, 311 { .soc_id = "r8a7796" }, 312 { .soc_id = "r8a77965" }, 313 { .soc_id = "r8a77970" }, 314 { .soc_id = "r8a77980" }, 315 { .soc_id = "r8a77990" }, 316 { .soc_id = "r8a77995" }, 317 { /* sentinel */ } 318 }; 319 320 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 321 { 322 const struct soc_device_attribute *soc = soc_device_match(soc_whitelist); 323 struct device *dev = &pdev->dev; 324 325 if (!soc) 326 return -ENODEV; 327 328 global_flags |= (unsigned long)soc->data; 329 330 dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL); 331 if (!dev->dma_parms) 332 return -ENOMEM; 333 334 /* value is max of SD_SECCNT. Confirmed by HW engineers */ 335 dma_set_max_seg_size(dev, 0xffffffff); 336 337 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops); 338 } 339 340 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 341 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 342 pm_runtime_force_resume) 343 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 344 tmio_mmc_host_runtime_resume, 345 NULL) 346 }; 347 348 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 349 .driver = { 350 .name = "renesas_sdhi_internal_dmac", 351 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 352 .of_match_table = renesas_sdhi_internal_dmac_of_match, 353 }, 354 .probe = renesas_sdhi_internal_dmac_probe, 355 .remove = renesas_sdhi_remove, 356 }; 357 358 module_platform_driver(renesas_internal_dmac_sdhi_driver); 359 360 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 361 MODULE_AUTHOR("Yoshihiro Shimoda"); 362 MODULE_LICENSE("GPL v2"); 363