1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DMA support for Internal DMAC with SDHI SD/SDIO controller 4 * 5 * Copyright (C) 2016-17 Renesas Electronics Corporation 6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/io-64-nonatomic-hi-lo.h> 13 #include <linux/mfd/tmio.h> 14 #include <linux/mmc/host.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/pagemap.h> 18 #include <linux/scatterlist.h> 19 #include <linux/sys_soc.h> 20 21 #include "renesas_sdhi.h" 22 #include "tmio_mmc.h" 23 24 #define DM_CM_DTRAN_MODE 0x820 25 #define DM_CM_DTRAN_CTRL 0x828 26 #define DM_CM_RST 0x830 27 #define DM_CM_INFO1 0x840 28 #define DM_CM_INFO1_MASK 0x848 29 #define DM_CM_INFO2 0x850 30 #define DM_CM_INFO2_MASK 0x858 31 #define DM_DTRAN_ADDR 0x880 32 33 /* DM_CM_DTRAN_MODE */ 34 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 35 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */ 36 #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4)) 37 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address */ 38 39 /* DM_CM_DTRAN_CTRL */ 40 #define DTRAN_CTRL_DM_START BIT(0) 41 42 /* DM_CM_RST */ 43 #define RST_DTRANRST1 BIT(9) 44 #define RST_DTRANRST0 BIT(8) 45 #define RST_RESERVED_BITS GENMASK_ULL(31, 0) 46 47 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 48 #define INFO1_CLEAR 0 49 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) 50 #define INFO1_DTRANEND1 BIT(17) 51 #define INFO1_DTRANEND0 BIT(16) 52 53 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 54 #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0) 55 #define INFO2_DTRANERR1 BIT(17) 56 #define INFO2_DTRANERR0 BIT(16) 57 58 /* 59 * Specification of this driver: 60 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 61 * - Since this SDHI DMAC register set has 16 but 32-bit width, we 62 * need a custom accessor. 63 */ 64 65 static unsigned long global_flags; 66 /* 67 * Workaround for avoiding to use RX DMAC by multiple channels. 68 * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use 69 * RX DMAC simultaneously, sometimes hundreds of bytes data are not 70 * stored into the system memory even if the DMAC interrupt happened. 71 * So, this driver then uses one RX DMAC channel only. 72 */ 73 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY 0 74 #define SDHI_INTERNAL_DMAC_RX_IN_USE 1 75 76 /* Definitions for sampling clocks */ 77 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 78 { 79 .clk_rate = 0, 80 .tap = 0x00000300, 81 }, 82 }; 83 84 static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = { 85 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 86 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 | 87 TMIO_MMC_HAVE_4TAP_HS400, 88 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 89 MMC_CAP_CMD23, 90 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT, 91 .bus_shift = 2, 92 .scc_offset = 0x1000, 93 .taps = rcar_gen3_scc_taps, 94 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 95 /* DMAC can handle 0xffffffff blk count but only 1 segment */ 96 .max_blk_count = 0xffffffff, 97 .max_segs = 1, 98 }; 99 100 static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = { 101 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 102 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 103 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 104 MMC_CAP_CMD23, 105 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT, 106 .bus_shift = 2, 107 .scc_offset = 0x1000, 108 .taps = rcar_gen3_scc_taps, 109 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 110 /* DMAC can handle 0xffffffff blk count but only 1 segment */ 111 .max_blk_count = 0xffffffff, 112 .max_segs = 1, 113 }; 114 115 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 116 { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, }, 117 { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_r8a7795_compatible, }, 118 { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_r8a7795_compatible, }, 119 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 120 {}, 121 }; 122 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 123 124 static void 125 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host, 126 int addr, u64 val) 127 { 128 writeq(val, host->ctl + addr); 129 } 130 131 static void 132 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 133 { 134 struct renesas_sdhi *priv = host_to_priv(host); 135 136 if (!host->chan_tx || !host->chan_rx) 137 return; 138 139 if (!enable) 140 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1, 141 INFO1_CLEAR); 142 143 if (priv->dma_priv.enable) 144 priv->dma_priv.enable(host, enable); 145 } 146 147 static void 148 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) { 149 u64 val = RST_DTRANRST1 | RST_DTRANRST0; 150 151 renesas_sdhi_internal_dmac_enable_dma(host, false); 152 153 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 154 RST_RESERVED_BITS & ~val); 155 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 156 RST_RESERVED_BITS | val); 157 158 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 159 160 renesas_sdhi_internal_dmac_enable_dma(host, true); 161 } 162 163 static void 164 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) { 165 struct renesas_sdhi *priv = host_to_priv(host); 166 167 tasklet_schedule(&priv->dma_priv.dma_complete); 168 } 169 170 static void 171 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 172 struct mmc_data *data) 173 { 174 struct scatterlist *sg = host->sg_ptr; 175 u32 dtran_mode = DTRAN_MODE_BUS_WIDTH | DTRAN_MODE_ADDR_MODE; 176 177 if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len, 178 mmc_get_dma_dir(data))) 179 goto force_pio; 180 181 /* This DMAC cannot handle if buffer is not 8-bytes alignment */ 182 if (!IS_ALIGNED(sg_dma_address(sg), 8)) 183 goto force_pio_with_unmap; 184 185 if (data->flags & MMC_DATA_READ) { 186 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 187 if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) && 188 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags)) 189 goto force_pio_with_unmap; 190 } else { 191 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 192 } 193 194 renesas_sdhi_internal_dmac_enable_dma(host, true); 195 196 /* set dma parameters */ 197 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE, 198 dtran_mode); 199 renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR, 200 sg_dma_address(sg)); 201 202 return; 203 204 force_pio_with_unmap: 205 dma_unmap_sg(&host->pdev->dev, sg, host->sg_len, mmc_get_dma_dir(data)); 206 207 force_pio: 208 host->force_pio = true; 209 renesas_sdhi_internal_dmac_enable_dma(host, false); 210 } 211 212 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 213 { 214 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 215 216 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 217 218 /* start the DMAC */ 219 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL, 220 DTRAN_CTRL_DM_START); 221 } 222 223 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) 224 { 225 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 226 enum dma_data_direction dir; 227 228 spin_lock_irq(&host->lock); 229 230 if (!host->data) 231 goto out; 232 233 if (host->data->flags & MMC_DATA_READ) 234 dir = DMA_FROM_DEVICE; 235 else 236 dir = DMA_TO_DEVICE; 237 238 renesas_sdhi_internal_dmac_enable_dma(host, false); 239 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir); 240 241 if (dir == DMA_FROM_DEVICE) 242 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 243 244 tmio_mmc_do_data_irq(host); 245 out: 246 spin_unlock_irq(&host->lock); 247 } 248 249 static void 250 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 251 struct tmio_mmc_data *pdata) 252 { 253 struct renesas_sdhi *priv = host_to_priv(host); 254 255 /* Disable DMAC interrupts, we don't use them */ 256 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK, 257 INFO1_MASK_CLEAR); 258 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK, 259 INFO2_MASK_CLEAR); 260 261 /* Each value is set to non-zero to assume "enabling" each DMA */ 262 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 263 264 tasklet_init(&priv->dma_priv.dma_complete, 265 renesas_sdhi_internal_dmac_complete_tasklet_fn, 266 (unsigned long)host); 267 tasklet_init(&host->dma_issue, 268 renesas_sdhi_internal_dmac_issue_tasklet_fn, 269 (unsigned long)host); 270 } 271 272 static void 273 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 274 { 275 /* Each value is set to zero to assume "disabling" each DMA */ 276 host->chan_rx = host->chan_tx = NULL; 277 } 278 279 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 280 .start = renesas_sdhi_internal_dmac_start_dma, 281 .enable = renesas_sdhi_internal_dmac_enable_dma, 282 .request = renesas_sdhi_internal_dmac_request_dma, 283 .release = renesas_sdhi_internal_dmac_release_dma, 284 .abort = renesas_sdhi_internal_dmac_abort_dma, 285 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 286 }; 287 288 /* 289 * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC 290 * implementation as others may use a different implementation. 291 */ 292 static const struct soc_device_attribute soc_whitelist[] = { 293 /* specific ones */ 294 { .soc_id = "r8a7795", .revision = "ES1.*", 295 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 296 { .soc_id = "r8a7796", .revision = "ES1.0", 297 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 298 /* generic ones */ 299 { .soc_id = "r8a774a1" }, 300 { .soc_id = "r8a77470" }, 301 { .soc_id = "r8a7795" }, 302 { .soc_id = "r8a7796" }, 303 { .soc_id = "r8a77965" }, 304 { .soc_id = "r8a77970" }, 305 { .soc_id = "r8a77980" }, 306 { .soc_id = "r8a77995" }, 307 { /* sentinel */ } 308 }; 309 310 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 311 { 312 const struct soc_device_attribute *soc = soc_device_match(soc_whitelist); 313 struct device *dev = &pdev->dev; 314 315 if (!soc) 316 return -ENODEV; 317 318 global_flags |= (unsigned long)soc->data; 319 320 dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL); 321 if (!dev->dma_parms) 322 return -ENOMEM; 323 324 /* value is max of SD_SECCNT. Confirmed by HW engineers */ 325 dma_set_max_seg_size(dev, 0xffffffff); 326 327 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops); 328 } 329 330 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 331 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 332 pm_runtime_force_resume) 333 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 334 tmio_mmc_host_runtime_resume, 335 NULL) 336 }; 337 338 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 339 .driver = { 340 .name = "renesas_sdhi_internal_dmac", 341 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 342 .of_match_table = renesas_sdhi_internal_dmac_of_match, 343 }, 344 .probe = renesas_sdhi_internal_dmac_probe, 345 .remove = renesas_sdhi_remove, 346 }; 347 348 module_platform_driver(renesas_internal_dmac_sdhi_driver); 349 350 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 351 MODULE_AUTHOR("Yoshihiro Shimoda"); 352 MODULE_LICENSE("GPL v2"); 353